Datasheet KSZ9893RNX (Microchip)

ManufacturerMicrochip
Description3-Port Gigabit Ethernet Switch with RGMII/MII/RMII Interface
Pages / Page11 / 1 — KSZ9893RNX. 3-Port Gigabit Ethernet Switch. with RGMII/MII/RMII …
File Format / SizePDF / 231 Kb
Document Languageenglish

KSZ9893RNX. 3-Port Gigabit Ethernet Switch. with RGMII/MII/RMII Interface. Highlights. Target Applications. Features

Datasheet KSZ9893RNX Microchip

Model Line for this Datasheet

Text Version of Document

KSZ9893RNX 3-Port Gigabit Ethernet Switch with RGMII/MII/RMII Interface Highlights
• Two Integrated PHY Ports - 1000BASE-T/100BASE-TX/10BASE-T IEEE 802.3 • Non-blocking wire-speed Ethernet switching fabric - Fast Link-up option significantly reduces link-up time • Full-featured forwarding and filtering control, includ- - Auto-negotiation and Auto-MDI/MDI-X support ing Access Control List (ACL) filtering - Energy-Efficient Ethernet (EEE) support with low- • Full VLAN and QoS support power idle mode and clock stoppage • Two ports with integrated 10/100/1000BASE-T PHYs - On-chip termination resistors and internal biasing for • One port with 10/100/1000 Ethernet MAC and differential pairs to reduce power configurable RGMII/MII/RMII interface - LinkMD® cable diagnostic capabilities for determining cable opens, shorts, and length • IEEE 802.1X port-based authentication support • One Configurable External MAC Port • EtherGreen™ power management features, - Reduced Gigabit Media Independent Interface including low power standby and IEEE 802.3az (RGMII) v2.0 • Flexible management interface options: SPI, I2C, - Reduced Media Independent Interface (RMII) v1.2 MIIM, and in-band management via any port with 50MHz reference clock input/output option • Commercial/Industrial temperature range support - Media Independent Interface (MII) in PHY/MAC mode • 64-pin VQFN (8 x 8mm) lead-free package • Advanced Switch Capabilities - IEEE 802.1Q VLAN support for 128 active VLAN
Target Applications
groups and the full range of 4096 VLAN IDs - IEEE 802.1p/Q tag insertion/removal on per port basis • Stand-alone 10/100/1000Mbps Ethernet switches - VLAN ID tag/untag options on per port or VLAN basis • VoIP infrastructure switches - IEEE 802.3x full-duplex flow control and half-duplex • Broadband gateways/firewalls back pressure collision control • Wi-Fi access points - IEEE 802.1X (Port-Based Network Access Control) • Integrated DSL/cable modems - IGMP v1/v2/v3 snooping for multicast packet filtering • Security/surveillance systems - IPv6 multicast listener discovery (MLD) snooping - IPv4/IPv6 QoS support, QoS/CoS packet prioritization • Industrial control/automation switches - 802.1p QoS packet classification with 4 priority queues • Networked measurement and control systems - Programmable rate limiting at ingress/egress ports - Broadcast storm protection
Features
- Four priority queues with dynamic packet mapping for IEEE 802.1p, IPv4 DIFFSERV, IPv6 Traffic Class • Switch Management Capabilities - MAC filtering function to filter or forward unknown uni- - 10/100/1000Mbps Ethernet switch basic functions: cast, multicast and VLAN packets frame buffer management, address look-up table, - Self-address filtering for implementing ring topologies queue management, MIB counters • Comprehensive Configuration Registers Access - Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 4096 entry forwarding - High-speed 4-wire SPI (up to 50MHz), I2C interfaces table with 128kByte frame buffer provide access to all internal registers - Jumbo packet support up to 9000 bytes - MII Management (MIIM, MDC/MDIO 2-wire) Interface - Port mirroring/monitoring/sniffing: provides access to all PHY registers ingress and/or egress traffic to any port - In-band management via any of the three ports - MIB counters for fully-compliant statistics gathering - I/O pin strapping facility to set certain register bits from 34 counters per port I/O pins at reset time - Tail tagging mode (one byte added before FCS) sup- - On-the-fly configurable control registers port at host port to inform the processor which ingress • Power Management port receives the packet and its priority - IEEE 802.3az Energy Efficient Ethernet (EEE) - Loopback modes for remote failure diagnostics - Energy detect power-down mode on cable disconnect - Rapid spanning tree protocol (RSTP) support for topol- - Dynamic clock tree control ogy management and ring/linear recovery - Unused ports can be individually powered down - Multiple spanning tree protocol (MSTP) support - Full-chip software power-down - Wake-on-LAN (WoL) standby power mode  2016 Microchip Technology Inc. DS00002318A-page 1 Document Outline Highlights Target Applications Features 1.0 Introduction 1.1 General Description FIGURE 1-1: Internal Block Diagram 2.0 Package Information 2.1 Package Drawings FIGURE 2-1: Package (Drawing) FIGURE 2-2: Package (Dimensions) FIGURE 2-3: Package (Land Pattern) Appendix A: PRODUCT BRIEF Revision History The Microchip Web Site Product Identification System Worldwide Sales and Service
PCB Design Analysis Software-NextDFM One-click Design Analysis for Manufacturability Layout Engineer Free Forever