Datasheet ADuM6420A, ADuM6421A, ADuM6422A (Analog Devices) - 6

ADuM6420A/ ADuM6421A/ ADuM6422A Data Sheet ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
All typical specifications are at TA = 25°C, VDD1 = VDDP = 5.0 V, VDD2 = VISO = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ (VDD1, VDDP) ≤ 5.5 V, 3.0 V ≤ (VDD2, VISO) ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. DC-to-DC Converters Static Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DC-TO-DC CONVERTERS SUPPLY Setpoint VISO 3.135 3.3 3.465 V IISO = 10 mA Line Regulation VISO (LINE) 20 mV/V IISO = 50 mA, VDD1 = 3.0 V to 3.6 V Load Regulation VISO (LOAD) 1 5 % IISO = 10 mA to 90 mA Output Ripple VISO (RIP) 50 mV p-p 20 MHz bandwidth, CBO = 0.1 µF| 10 µF, IISO = 90 mA Output Noise VISO (NOISE) 130 mV p-p CBO = 0.1 µF| 10 µF, IISO = 90 mA Switching Frequency fOSC 180 MHz Pulse-Width Modulation Frequency fPWM 625 kHz Output Supply1 IISO (MAX) 100 mA 3.465 V > VISO > 3.135 V, TA ≤ +105°C Efficiency at IISO (MAX) 34 % IISO = 100 mA VDDP Supply Current No VISO Load IDDP (Q) 14 20 mA Full VISO Load IDDP (MAX) mA Thermal Shutdown Shutdown Temperature 154 °C Thermal Hysteresis 10 °C 1 Maximum VISO output current is derated by 1.75 mA/°C for TA > 85ºC.
Table 7. Data Channel Supply Current Specifications 1 Mbps 10 Mbps 100 Mbps Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT CL = 0 pF ADuM6420A IDD1 4.9 8.7 5.5 9.5 8.0 12.2 mA IDD2 1.4 2.5 2.1 3.4 7.5 11 mA ADuM6421A IDD1 4.2 8.4 4.5 8.5 8.0 12.0 mA IDD2 2.1 4.4 2.7 5.6 8.0 11.6 mA ADuM6422A IDD1 3.3 6.0 3.9 6.2 8.3 12.0 mA IDD2 3.0 6.0 3.7 6.2 8.5 12 mA
Table 8. Switching Specifications Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SWITCHING SPECIFICATIONS Pulse Width PW 10 ns Within PWD limit Data Rate 100 Mbps Within PWD limit Propagation Delay tPHL, tPLH 7.0 10 15 ns 50% input to 50% output Pulse Width Distortion PWD 1.0 5.0 ns |tPLH − tPHL| Change vs. Temperature 1.5 ps/°C Propagation Delay Skew tPSK 8.0 ns Between any two units at the same temperature, voltage, and load Channel Matching Codirectional tPSKCD 1.0 5.0 ns Opposing Direction tPSKOD 1.0 5.0 ns Jitter 816 ps p-p Rev. 0 | Page 6 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY ELECTRICAL CHARACTERISTICS—3.3 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—2.5 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY ELECTRICAL CHARACTERISTICS—1.8 V OPERATION DIGITAL ISOLATOR CHANNELS ONLY PACKAGE CHARACTERISTICS REGULATORY APPROVALS INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-11 INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TRUTH TABLE TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT THERMAL ANALYSIS PROPAGATION DELAY RELATED PARAMETERS EMI CONSIDERATIONS POWER CONSUMPTION INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example OUTLINE DIMENSIONS ORDERING GUIDE