Datasheet ADSP-TS101S (Analog Devices) - 8

ADSP-TS101S
The DMA controller also supports two-dimensional transfers. The DMA controller can access and transfer two-dimensional memory arrays on any DMA transmit or receive channel. These transfers are implemented with index, count, and modify regis- ters for both the X and Y dimensions.
ADSP-TS101 #7 ADSP-TS101 #6 ADSP-TS101 #5 L S ADSP-TS101 #4 O S ADSP-TS101 #3 R E A T R T ADSP-TS101 #2 N D A O D D C A ADSP-TS101 #1 001 ID2–0 BR7–2,0 RESET BR1 ADDR31–0 CLKS/REFS DATA63–0 LINK CONTROL ADSP-TS101 #0 L S O S R E A T R T 000 ID2–0 BR7–1 N D A O D D BR0 C A RESET RESET ADDR31–0 ADDR CLKS/REFS DATA63–0 GLOBAL DATA MEMORY RD OE AND WRH/L PERIPHERALS WE SCLK_P (OPTIONAL) ACK ACK MS1–0 CS CLOCK BUSLOCK LCLK_P BMS CS BOOT REFERENCE CPA S/LCLK_N ADDR EPROM VOLTAGE DPA (OPTIONAL) VREF DATA BOFF LCLKRAT2–0 DMAR3–0 SCLKFREQ CLOCK BRST HBR IRQ3–0 HOST HBG PROCESSOR FLAG3–0 MSH INTERFACE LINK FLYBY ADDR (OPTIONAL) IOEN DATA LINK LXDAT7–0 MSSD LXCLKIN CS DEVICES SDRAM RAS (4 MAX) LXCLKOUT RAS MEMORY (OPTIONAL) CAS LXDIR CAS (OPTIONAL) LDQM DQM HDQM SDWE TMR0E WE SDCKE BM CKE SDA10 A10 CONTROLIMP2–0 ADDR DS2–0 CONTROL DATA CLK
Figure 4. Shared Memory Multiprocessing System The DMA controller performs the following DMA operations: external memory. These transfers only use handshake • External port block transfers. Four dedicated bidirectional mode protocol. DMA priority rotates between the four DMA channels transfer blocks of data between the DSP’s receive channels. internal memory and any external memory or memory- • AutoDMA transfers. Two dedicated unidirectional DMA mapped peripheral on the external bus. These transfers channels transfer data received from an external bus master support master mode and handshake mode protocols. to internal memory or to link port I/O. These transfers only • Link port transfers. Eight dedicated DMA channels (four use slave mode protocol, and an external bus master must transmit and four receive) transfer quad word data only initiate the transfer. between link ports and between a link port and internal or Rev. D | Page 8 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide