Datasheet MAX1472 (Maxim) - 3
| Manufacturer | Maxim |
| Description | 300MHz-to-450MHz Low-Power, Crystal-Based ASK Transmitter |
| Pages / Page | 9 / 3 — 300MHz-to-450MHz Low-Power,. Crystal-Based ASK Transmitter. MAX1472. … |
| File Format / Size | PDF / 169 Kb |
| Document Language | English |
300MHz-to-450MHz Low-Power,. Crystal-Based ASK Transmitter. MAX1472. ELECTRICAL CHARACTERISTICS (continued). PARAMETER. SYMBOL
Model Line for this Datasheet
Text Version of Document
300MHz-to-450MHz Low-Power, Crystal-Based ASK Transmitter MAX1472 ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, output power is referenced to 50Ω, VDD = 2.1V to 3.6V, VENABLE = VDD, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 2.7V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PHASE-LOCKED LOOP PERFORMANCE
VCO Gain 330 MHz/V fOFFSET =100kHz -84 fRF = 315MHz fOFFSET = 1MHz -91 Phase Noise dBc/Hz fOFFSET =100kHz -82 fRF = 433MHz fOFFSET = 1MHz -89 fRF = 315MHz -50 Maximum Carrier Harmonics dBc fRF = 433MHz -50 fRF = 315MHz -75 Reference Spur dBc fRF = 433MHz -81 Loop Bandwidth 1.6 MHz Crystal Frequency fXTAL fRF / 32 MHz Oscillator Input Capacitance From each XTAL pin to GND 6.2 pF Frequency Pushing by VDD 3 ppm/V
DIGITAL INPUTS
Data Input High VIH V D D - 0.25 V Data Input Low VIL 0.25 V Maximum Input Current 2 nA Pulldown Current 25 µA
Note 1:
100% tested at TA = +25°C. Guaranteed by design and characterization over temperature.
Note 2:
50% duty cycle at 10kHz data.
Note 3:
Guaranteed by design and characterization, not production tested.
Note 4:
Generally limited by PC board layout.
Note 5:
Output power can be adjusted with external resistor.
Note 6:
Guaranteed by design and characterization at fRF = 315MHz.
Note 7:
VENABLE < VIL to VENABLE > VIH. fOFFSET is defined as the frequency deviation from the desired carrier frequency.
Note 8:
VENABLE > VIH, VDATA > VIH, Efficiency = POUT/(VDD x IDD).
Note 9:
VENABLE > VIH, DATA toggled from VIL to VIH, 10kHz, 50% duty cycle, Efficiency = POUT/(VDD x IDD).
3
(Typical Application Circuit, output power is referenced to 50Ω, VDD = 2.1V to 3.6V, VENABLE = VDD, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VDD = 2.7V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PHASE-LOCKED LOOP PERFORMANCE
VCO Gain 330 MHz/V fOFFSET =100kHz -84 fRF = 315MHz fOFFSET = 1MHz -91 Phase Noise dBc/Hz fOFFSET =100kHz -82 fRF = 433MHz fOFFSET = 1MHz -89 fRF = 315MHz -50 Maximum Carrier Harmonics dBc fRF = 433MHz -50 fRF = 315MHz -75 Reference Spur dBc fRF = 433MHz -81 Loop Bandwidth 1.6 MHz Crystal Frequency fXTAL fRF / 32 MHz Oscillator Input Capacitance From each XTAL pin to GND 6.2 pF Frequency Pushing by VDD 3 ppm/V
DIGITAL INPUTS
Data Input High VIH V D D - 0.25 V Data Input Low VIL 0.25 V Maximum Input Current 2 nA Pulldown Current 25 µA
Note 1:
100% tested at TA = +25°C. Guaranteed by design and characterization over temperature.
Note 2:
50% duty cycle at 10kHz data.
Note 3:
Guaranteed by design and characterization, not production tested.
Note 4:
Generally limited by PC board layout.
Note 5:
Output power can be adjusted with external resistor.
Note 6:
Guaranteed by design and characterization at fRF = 315MHz.
Note 7:
VENABLE < VIL to VENABLE > VIH. fOFFSET is defined as the frequency deviation from the desired carrier frequency.
Note 8:
VENABLE > VIH, VDATA > VIH, Efficiency = POUT/(VDD x IDD).
Note 9:
VENABLE > VIH, DATA toggled from VIL to VIH, 10kHz, 50% duty cycle, Efficiency = POUT/(VDD x IDD).
3
