Datasheet VNF1048F (STMicroelectronics) - 3
| Manufacturer | STMicroelectronics |
| Description | High-side switch Controller with intelligent fuse protection for 12 V, 24 V and 48 V automotive applications |
| Pages / Page | 52 / 3 — VNF1048F. Block diagram and pin description. Table 1. Pin functions. … |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
VNF1048F. Block diagram and pin description. Table 1. Pin functions. Name. Function. DS13084. Rev 6. page 3/52
Model Line for this Datasheet
Text Version of Document
VNF1048F Block diagram and pin description Table 1. Pin functions Name Function
VS Input supply pin. Connect to the 12 V, 24 V, 48 V battery voltage. CP Charge pump output. CP2P Charge pump–Positive terminal of the flying capacitor CP2. CP2M Charge pump–Negative terminal of the flying capacitor CP2. CP1P Charge pump–Positive terminal of the flying capacitor CP1. CP1M Charge pump–Negative terminal of the flying capacitor CP1. GND Ground connection. VSPI DC supply input for the SPI interface. 3.3 V and 5 V compatible. Output of the 3.3 V internal LDO voltage regulator (logic and I/O supply). V3V3 Connect a low ESR capacitor (1 μF) close to this pin. CSN Chip select not (active low) for SPI communication. It is the selection pin of the device. CMOS compatible input. SDI Serial data input for SPI communication. Data is transferred serially into the device on SCK rising edge. SDO Serial data output for SPI communication. Data is transferred serially out of the device on SCK falling edge. SCK Serial clock for SPI communication. It is a CMOS compatible input. Open drain logic output. Diagnostic feedback. DIAG = '0' if (SR1.WAKEUPM = '1') or (GSB.DIAGS = '1') or DIAG (GSB.DE = '1') else '1' Active high input pin compatible with 3.3 V and 5 V CMOS; it causes transitions to states where the registers are HWLO locked from writing. ISNS_P Current sense amplifier positive input. ISNS_N Current sense amplifier negative input. HS_GATE Output of the gate driver for the external FET. OUT External FET source connection. NTC Positive input pin for external NTC resistor. NTC_M Negative input pin for external NTC resistor. TEST1 Test mode pin 1- must be connected to ground. TEST2 Test mode pin 2- must be connected to ground.
DS13084
-
Rev 6 page 3/52
Document Outline 1 Block diagram and pin description 2 Electrical specification 2.1 Absolute maximum ratings 2.2 Thermal data 2.3 Main electrical characteristics 3 eFuse function 4 Self Test 4.1 Current Sense Self Test 4.2 External FET VDS Detection Self Test 4.3 External FET Stuck-on Self Test 5 Protections 5.1 Battery undervoltage shutdown 5.2 Device overtemperature shutdown 5.3 External MOSFET overtemperature shutdown 5.4 External MOSFET desaturation shut-down 5.5 Hard short circuit latch-off 5.6 Current vs time latch-off 5.7 Low Current Bypass desaturation shut-down 6 SPI functional description 6.1 SPI Communication 6.2 Signal description 6.3 SPI protocol 6.4 Operating code definition 6.5 Write mode 6.6 Read mode 6.7 Read and clear status command 6.8 SPI device information 6.9 Special commands 6.10 Global status byte 6.11 Address map 6.12 ROM memory map 6.13 Control registers 6.14 Status registers 6.15 Timeout watchdog 7 Operating modes 7.1 State Diagram 7.2 PowerON mode 7.3 Stand-by mode 7.4 WakeUp mode 7.5 Unlocked mode 7.6 Locked mode 7.7 Self-test mode 8 Application information 9 Package information 9.1 QFN32L 5x5 package information Revision history
VS Input supply pin. Connect to the 12 V, 24 V, 48 V battery voltage. CP Charge pump output. CP2P Charge pump–Positive terminal of the flying capacitor CP2. CP2M Charge pump–Negative terminal of the flying capacitor CP2. CP1P Charge pump–Positive terminal of the flying capacitor CP1. CP1M Charge pump–Negative terminal of the flying capacitor CP1. GND Ground connection. VSPI DC supply input for the SPI interface. 3.3 V and 5 V compatible. Output of the 3.3 V internal LDO voltage regulator (logic and I/O supply). V3V3 Connect a low ESR capacitor (1 μF) close to this pin. CSN Chip select not (active low) for SPI communication. It is the selection pin of the device. CMOS compatible input. SDI Serial data input for SPI communication. Data is transferred serially into the device on SCK rising edge. SDO Serial data output for SPI communication. Data is transferred serially out of the device on SCK falling edge. SCK Serial clock for SPI communication. It is a CMOS compatible input. Open drain logic output. Diagnostic feedback. DIAG = '0' if (SR1.WAKEUPM = '1') or (GSB.DIAGS = '1') or DIAG (GSB.DE = '1') else '1' Active high input pin compatible with 3.3 V and 5 V CMOS; it causes transitions to states where the registers are HWLO locked from writing. ISNS_P Current sense amplifier positive input. ISNS_N Current sense amplifier negative input. HS_GATE Output of the gate driver for the external FET. OUT External FET source connection. NTC Positive input pin for external NTC resistor. NTC_M Negative input pin for external NTC resistor. TEST1 Test mode pin 1- must be connected to ground. TEST2 Test mode pin 2- must be connected to ground.
DS13084
-
Rev 6 page 3/52
Document Outline 1 Block diagram and pin description 2 Electrical specification 2.1 Absolute maximum ratings 2.2 Thermal data 2.3 Main electrical characteristics 3 eFuse function 4 Self Test 4.1 Current Sense Self Test 4.2 External FET VDS Detection Self Test 4.3 External FET Stuck-on Self Test 5 Protections 5.1 Battery undervoltage shutdown 5.2 Device overtemperature shutdown 5.3 External MOSFET overtemperature shutdown 5.4 External MOSFET desaturation shut-down 5.5 Hard short circuit latch-off 5.6 Current vs time latch-off 5.7 Low Current Bypass desaturation shut-down 6 SPI functional description 6.1 SPI Communication 6.2 Signal description 6.3 SPI protocol 6.4 Operating code definition 6.5 Write mode 6.6 Read mode 6.7 Read and clear status command 6.8 SPI device information 6.9 Special commands 6.10 Global status byte 6.11 Address map 6.12 ROM memory map 6.13 Control registers 6.14 Status registers 6.15 Timeout watchdog 7 Operating modes 7.1 State Diagram 7.2 PowerON mode 7.3 Stand-by mode 7.4 WakeUp mode 7.5 Unlocked mode 7.6 Locked mode 7.7 Self-test mode 8 Application information 9 Package information 9.1 QFN32L 5x5 package information Revision history
