Datasheet AD8343 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | DC-to-2.5 GHz High IP3 Active Mixer |
| Pages / Page | 32 / 3 — AD8343. SPECIFICATIONS BASIC OPERATING INSTRUCTIONS. Table 1. Parameter … |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
AD8343. SPECIFICATIONS BASIC OPERATING INSTRUCTIONS. Table 1. Parameter Conditions/Comments. Min. Typ. Max. Unit
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AD8343 SPECIFICATIONS BASIC OPERATING INSTRUCTIONS
VS = 5.0 V, TA = 25°C, unless otherwise noted.
Table 1. Parameter Conditions/Comments Min Typ Max Unit
INPUT INTERFACE (INPP, INPM) Differential Open Emitter DC Bias Voltage Internally generated 1.1 1.2 1.3 V Operating Current Each Input (IO) Current set by R3, R4; see Figure 72 5 17.6 20 mA Value of Bias Setting Resistor1 1% bias resistors; R3, R4; see Figure 72 68.1 Ω Port Differential Impedance f = 50 MHz; R3 and R4 = 68.1 Ω; see Figure 57 5.6 + j 1.4 Ω OUTPUT INTERFACE (OUTP, OUTM) Differential Open Collector DC Bias Voltage Externally applied 4.5 5 5.5 V Voltage Swing Collector bias (VS) = VPOS 1.65 VS ± 1 VS + 2 V Operating Current Each Output Same as input current IO mA Port Differential Impedance f = 50 MHz; see Figure 60 900 − j 77 Ω LO INTERFACE (LOIP, LOIM) Differential Common Base Stage DC Bias Voltage2 Internally generated; (port is typically ac-coupled) 300 360 450 mV LO Input Power 50 Ω impedance; see Figure 65 −12 −10 −3 dBm Port Differential Reflection Coefficient See Figure 64 −10 dB POWER-DOWN INTERFACE (PWDN) PWDN Threshold Assured on VS − 1.5 V Assured off VS − 0.5 V PWDN Response Time3 Time from device on to off; see Figure 52 2.2 μs Time from device off to on; see Figure 53 500 ns PWDN Input Bias Current PWDN = 0 V (device on) −160 −250 μA PWDN = 5 V (device off ) 0 μA POWER SUPPLY Supply Voltage Range 4.5 5.0 5.5 V Total Quiescent Current R3 and R4 = 68.1 Ω; see Figure 72 50 60 mA Over temperature 75 mA Powered-Down Current VS = 5.5 V 20 95 μA VS = 4.5 V 6 15 μA Over temperature; VS = 5.5 V 50 150 μA 1 The balance in the bias current in the two legs of the mixer input is important to applications where a low feedthrough of the local oscillator (LO) is critical. 2 This voltage is proportional to absolute temperature (PTAT). See the DC Coupling the LO section for more information regarding this interface. 3 Response time until device meets all specified conditions. Rev. B | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BASIC OPERATING INSTRUCTIONS TYPICAL AC PERFORMANCE TYPICAL ISOLATION PERFORMANCE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVER CHARACTERISTICS TRANSMIT CHARACTERISTICS CIRCUIT DESCRIPTION DC INTERFACES BIASING AND DECOUPLING (VPOS, DCPL) POWER-DOWN INTERFACE (PWDN) AC INTERFACES INPUT INTERFACE (INPP AND INPM) SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION INPUT MATCHING CONSIDERATIONS INPUT BIASING CONSIDERATIONS OUTPUT INTERFACE (OUTP, OUTM) OUTPUT MATCHING CONSIDERATIONS OUTPUT BIASING CONSIDERATIONS INPUT AND OUTPUT STABILITY CONSIDERATIONS LOCAL OSCILLATOR INPUT INTERFACE (LOIP, LOIM) DC COUPLING THE LO A STEP-BY-STEP APPROACH TO IMPEDANCE MATCHING Circuit Setup Establish Target Impedance Measure AD8343 Differential Impedance at Location of First Matching Component Design the Matching Network Transfer the Matching Network to the Final Design APPLICATIONS DOWNCONVERTING MIXER UPCONVERTING MIXER EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
AD8343 SPECIFICATIONS BASIC OPERATING INSTRUCTIONS
VS = 5.0 V, TA = 25°C, unless otherwise noted.
Table 1. Parameter Conditions/Comments Min Typ Max Unit
INPUT INTERFACE (INPP, INPM) Differential Open Emitter DC Bias Voltage Internally generated 1.1 1.2 1.3 V Operating Current Each Input (IO) Current set by R3, R4; see Figure 72 5 17.6 20 mA Value of Bias Setting Resistor1 1% bias resistors; R3, R4; see Figure 72 68.1 Ω Port Differential Impedance f = 50 MHz; R3 and R4 = 68.1 Ω; see Figure 57 5.6 + j 1.4 Ω OUTPUT INTERFACE (OUTP, OUTM) Differential Open Collector DC Bias Voltage Externally applied 4.5 5 5.5 V Voltage Swing Collector bias (VS) = VPOS 1.65 VS ± 1 VS + 2 V Operating Current Each Output Same as input current IO mA Port Differential Impedance f = 50 MHz; see Figure 60 900 − j 77 Ω LO INTERFACE (LOIP, LOIM) Differential Common Base Stage DC Bias Voltage2 Internally generated; (port is typically ac-coupled) 300 360 450 mV LO Input Power 50 Ω impedance; see Figure 65 −12 −10 −3 dBm Port Differential Reflection Coefficient See Figure 64 −10 dB POWER-DOWN INTERFACE (PWDN) PWDN Threshold Assured on VS − 1.5 V Assured off VS − 0.5 V PWDN Response Time3 Time from device on to off; see Figure 52 2.2 μs Time from device off to on; see Figure 53 500 ns PWDN Input Bias Current PWDN = 0 V (device on) −160 −250 μA PWDN = 5 V (device off ) 0 μA POWER SUPPLY Supply Voltage Range 4.5 5.0 5.5 V Total Quiescent Current R3 and R4 = 68.1 Ω; see Figure 72 50 60 mA Over temperature 75 mA Powered-Down Current VS = 5.5 V 20 95 μA VS = 4.5 V 6 15 μA Over temperature; VS = 5.5 V 50 150 μA 1 The balance in the bias current in the two legs of the mixer input is important to applications where a low feedthrough of the local oscillator (LO) is critical. 2 This voltage is proportional to absolute temperature (PTAT). See the DC Coupling the LO section for more information regarding this interface. 3 Response time until device meets all specified conditions. Rev. B | Page 3 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS BASIC OPERATING INSTRUCTIONS TYPICAL AC PERFORMANCE TYPICAL ISOLATION PERFORMANCE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVER CHARACTERISTICS TRANSMIT CHARACTERISTICS CIRCUIT DESCRIPTION DC INTERFACES BIASING AND DECOUPLING (VPOS, DCPL) POWER-DOWN INTERFACE (PWDN) AC INTERFACES INPUT INTERFACE (INPP AND INPM) SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION INPUT MATCHING CONSIDERATIONS INPUT BIASING CONSIDERATIONS OUTPUT INTERFACE (OUTP, OUTM) OUTPUT MATCHING CONSIDERATIONS OUTPUT BIASING CONSIDERATIONS INPUT AND OUTPUT STABILITY CONSIDERATIONS LOCAL OSCILLATOR INPUT INTERFACE (LOIP, LOIM) DC COUPLING THE LO A STEP-BY-STEP APPROACH TO IMPEDANCE MATCHING Circuit Setup Establish Target Impedance Measure AD8343 Differential Impedance at Location of First Matching Component Design the Matching Network Transfer the Matching Network to the Final Design APPLICATIONS DOWNCONVERTING MIXER UPCONVERTING MIXER EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
