Datasheet PIC16C781, PIC16C782 (Microchip)
| Manufacturer | Microchip |
| Description | 8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC |
| Pages / Page | 188 / 1 — PIC16C781/782. 8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP,. … |
| File Format / Size | PDF / 4.1 Mb |
| Document Language | English |
PIC16C781/782. 8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP,. Comparators and PSMC. Microcontroller Core Features:
Model Line for this Datasheet
Text Version of Document
PIC16C781.book Page 1 Tuesday, January 29, 2013 3:29 PM
PIC16C781/782 8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC Microcontroller Core Features: Microcontroller Core Features (Continued):
• High performance RISC CPU • Low power, high speed CMOS EPROM • Only 35 single word instructions to learn technology • All single cycle instructions except for program • Fully static design branches which are two cycle • Low power consumption: • Direct, indirect and relative addressing modes - < 2 mA @ 5V, 4 MHz - Operating speed: DC - 20 MHz clock input - < 1 A typical standby current. DC - 200 ns instruction cycle
Pin Diagram Program Data Memory Device Memory PDIP, Windowed CERDIP, SOIC, SSOP X8 X14
RA0/AN0/OPA+ PIC16C781 1K 128 •1 1 20 RB3/AN7/OPA
P
RA1/AN1/OPA- 2 2
I
19 RB2/AN6
C1
RA4/T0CKI PIC16C782 2K 128 3 3 18 RA7/OSC1/CLKIN RA5/MCLR/VPP 4 4
6C
17 RA6/OSC2/CLKOUT/T1CKI 17 • 8-level deep hardware stack VSS 5 5
781
16 VDD AVSS 6 6 15 AVDD 15 • Interrupt capability (up to 8 internal/external RA2/AN2/VREF2 7 7
/78
14 RB7/C2/PSMC1B/T1G RA3/AN3/VREF1 8 8 13 RB6/C1/PSMC1A interrupt sources)
2
RB0/INT/AN4/VR 9 9 12 RB5 • 16 I/O pins: RB1/AN5/VDAC 10 11 RB4 - Individual direction control (13 pins) - Input only (3 pins), low leakage (2 pins)
Peripheral Features:
- Digital/Analog inputs (8 pins) • Programmable PORTB interrupt-on-change (8 pins) • Timer0: 8-bit timer/counter with 8-bit prescaler • Programmable PORTB weak pull-ups (8 pins) • Enhanced Timer1: • Power-on Reset (POR) - 16-bit timer/counter with prescaler • Power-up Timer (PWRT) and - External Gate Input mode Oscillator Start-up Timer (OST) - Option to use OSC1 and OSC2 in LP mode • Watchdog Timer (WDT) with a software enabled as Timer1 oscillator, if INTRC oscillator mode option and its own on-chip RC oscillator for selected reliable operation • Analog-to-Digital Converter (ADC):
• Programmable Brown-out Reset (BOR) - 8-bit resolution • Programmable Low Voltage Detection (LVD) - Programmable 8-channel input • Internal/external MCLR - Internal voltages available for self- • Programmable code protection diagnostics • Power saving SLEEP mode • Digital-to-Analog Converter (DAC): • Selectable oscillator options: - 8-bit resolution HS, XT, LP, EC, RC, INTRC (4 MHz/37 kHz) - Reference from AVDD, VREF1, or VR module • In-Circuit Serial Programming™ (ISCP™) - Output configurable to VDAC pin, Compara- • Program Memory Read (PMR) capability tors, and ADC reference • Four user programmable ID locations • Operational Amplifier module (OPA): • Wide operating voltage range: - Firmware initiated input offset voltage Auto Calibration module - 2.5V to 5.5V for commercial and industrial temperature ranges - Low leakage inputs - Extended temperature range available - Programmable Gain Bandwidth Product (GBWP) 2001-2013 Microchip Technology Inc.
Preliminary
DS41171B-page 1 Document Outline Microcontroller Core Features: Microcontroller Core Features (Continued): Peripheral Features: Peripheral Features (Continued): Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: PIC16C781 BLOCK DIAGRAM FIGURE 1-2: PIC16C782 BLOCK DIAGRAM FIGURE 1-3: Analog Signal Multiplexing Diagram 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: PIC16C781 PROGRAM MEMORY MAP AND STACK FIGURE 2-2: PIC16C782 PROGRAM MEMORY MAP AND STACK 2.2 Data Memory Organization FIGURE 2-3: REGISTER FILE MAP 2.2.1 General Purpose register file 2.2.2 Special Function Registers TABLE 2-1: PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY 2.3 STATUS Register Register 2-1: Status REGISTER (STATUS: 03h, 83h, 103h, 183h) 2.4 OPTION_REG Register Register 2-2: OPTION Register (OPTION_REG: 81h, 181h) 2.5 INTCON Register Register 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh) 2.6 PIE1 Register Register 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER (PIE1: 8Ch) 2.7 PIR1 Register Register 2-5: PERIPHERAL INTERRUPT REGISTER (PIR1 0Ch) 2.8 PCON Register Register 2-6: POWER CONTROL REGISTER (PCON: 8Eh) 2.9 PCL and PCLATH 2.9.1 Program Memory Paging 2.10 Stack 2.11 INDF EXAMPLE 2-1: How to Clear RAM Using Indirect Addressing FIGURE 2-4: Loading of PC in Different Situations FIGURE 2-5: Direct/Indirect Addressing 2.12 Effect of RESET on Core Registers TABLE 2-2: Effect of reset on core registers 3.0 I/o Ports 3.1 I/O Port Analog/Digital Mode Register 3-1: Analog select register (ansel: 9Dh) 3.2 PORTA and the TRISA Register EXAMPLE 3-1: Initializing PortA 3.2.1 TRISA, ANSEL, and control precedence FIGURE 3-1: Block Diagram of RA0/AN0/OPA+ PIN FIGURE 3-2: Block Diagram of RA1/AN1/OPA- PIN FIGURE 3-3: Block Diagram of RA2/AN2/Vref2 PIN FIGURE 3-4: Block Diagram of RA3/AN3/Vref1 PIN FIGURE 3-5: Block Diagram of RA4/T0CKI PIN FIGURE 3-6: Block Diagram of RA5/MCLR/Vpp PIN FIGURE 3-7: Block Diagram of RA6/OSC2/CLKOUT/T1CKI PIN FIGURE 3-8: Block Diagram of RA7/OSC1/CLKIN PIN TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA 3.3 PORTB and the TRISB Register EXAMPLE 3-2: INITIALIZING PORTB 3.3.1 PortB Weak Pull-up 3.3.2 PortB Interrupt-On-Change Register 3-2: Weak Pull-Up PORTB Register (WPUB: 95h) Register 3-3: Interrupt-on-Change PORTB Register (IOCB: 96h) 3.3.3 TRISB, ANSEL, and control precedence FIGURE 3-9: Block Diagram of RB0/INT/AN4/Vr PIN FIGURE 3-10: Block Diagram of RB1/AN5/Vdac PIN FIGURE 3-11: Block Diagram of RB2/AN6 PIN FIGURE 3-12: Block Diagram of RB3/AN7/OPA PIN FIGURE 3-13: Block Diagram of RB4 PIN FIGURE 3-14: Block Diagram of RB5 pin FIGURE 3-15: Block Diagram of RB6/C1/PSMC1A PIN FIGURE 3-16: Block Diagram of RB7/C2/PSMC1B/T1G PIN TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB 4.0 Program Memory Read (Pmr) 4.1 PMCON1 Register 4.2 PMDATH and PMDATL Registers Register 4-1: program memory read Control Register 1 (pmCON1: 18Ch) Register 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh) Register 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch) Register 4-4: PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh) Register 4-5: PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh) 4.3 Reading the EPROM Program Memory EXAMPLE 4-1: OTP PROGRAM MEMORY READ 4.4 Program Memory Read With Code Protect Set TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PMR FIGURE 4-1: Program Memory Read Cycle Execution 5.0 Timer0 Module 5.1 Timer0 Operation EXAMPLE 5-1: INITIALIZING TIMER0 FIGURE 5-1: Timer0 Block Diagram 5.2 Prescaler 5.2.1 Switching Prescaler Assignment 5.3 Timer0 Interrupt 5.4 Effects of RESET FIGURE 5-2: Block Diagram of the Timer0/WDT Prescaler TABLE 5-1: Registers Associated with Timer0 6.0 Timer1 Module with gate Control 6.1 Timer1 Operation EXAMPLE 6-1: Timer1 Initialization 6.2 Control Register T1CON Register 6-1: TIMER1 CONTROL REGISTER (T1CON: ADDRESS 10h) FIGURE 6-1: Timer1 Incrementing Edge FIGURE 6-2: Timer1 ON THE PIC16C781/782 Block Diagram 6.3 Timer1 Oscillator for the PIC16C781/782 6.4 Timer1 Interrupt 6.5 Effects of RESET TABLE 6-1: summary of REGISTERS ASSOCIATED WITH TIMER1 7.0 Voltage Reference Module (Vr) 7.1 Effects of RESET 7.2 Registers Associated with Vr Register 7-1: Voltage Reference Control Register (REFCON: 9Bh) TABLE 7-1: Summary of Registers Associated with Vr 8.0 programmable LOW Voltage Detect MODULE (PLVD) FIGURE 8-1: Typical Low Voltage Detect Application 8.1 Control Register 8.2 Operation FIGURE 8-2: Low Voltage Detect Block Diagram 8.2.1 Setting Up the PLVD Module FIGURE 8-3: Low Voltage Detect waveforms Register 8-1: programmable LOW VOLTAGE DETECT Register (LVDCON: 9Ch) EXAMPLE 8-1: PLVD EXAMPLE 8.3 Operation During SLEEP 8.4 Effects of a RESET 8.5 Low Voltage Detect Registers TABLE 8-1: Summary of Registers Associated with LOW voltage detect 9.0 Analog-to-digital Converter (Adc) Module FIGURE 9-1: ADC Module Block Diagram 9.1 Control Registers 9.1.1 ADCON0 Register Register 9-1: ADC Control register 0 (adcon0: 1fh) 9.1.2 ADCON1 Register 9.1.3 ADRES REGISTER Register 9-2: ADC RESULT REGISTER (ADRES: 1Eh) Register 9-3: ADC control register 1 (adcon1: 9Fh) 9.2 Configuring the ADC Module 9.2.1 CONFIGURING ANALOG PORT PINS 9.2.2 CONFIGURING THE REFERENCE VOLTAGES 9.2.3 SELECTING THE ADC CONVERSION CLOCK TABLE 9-1: TAD vs. DEVICE OPERATING FREQUENCIES: PIC16C781/782 9.2.4 Initiating a Conversion 9.3 ADC Acquisition Requirements EQUATION 9-1: ADC MINIMUM CHARGING TIME EXAMPLE 9-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME FIGURE 9-2: Analog Input Model 9.4 ADC Configuration and Conversion EXAMPLE 9-2: ADC Conversion 9.4.1 Faster Conversion/Lower Resolution Trade-off 9.5 ADC Operation During SLEEP 9.6 ADC Accuracy/Error 9.6.1 Clock Noise 9.7 Effects of a RESET 9.8 Connection Considerations 9.9 Transfer Function 9.10 References FIGURE 9-3: ADC Transfer Function FIGURE 9-4: Flow chart of ADC Operation TABLE 9-2: Registers/Bits Associated with ADC, PIC16C781/782 10.0 Digital-to-analog Converter (DAC) Module 10.1 Control Registers Register 10-1: DIGITAL-TO-ANALOG CONVERTER CONTROL REGISTER0 (DACON0: 11Fh) Register 10-2: DIGITAL-TO-ANALOG CONVERTER REGISTER (DAC: 11Eh) 10.2 Control Register FIGURE 10-1: DAC Converter Block Diagram 10.3 DAC Configuration EXAMPLE 10-1: DAC configuration 10.4 Effects of RESET 10.5 DAC Module Accuracy/Error FIGURE 10-2: DAC TRANSFER FUNCTION TABLE 10-1: Registers/Bits Associated with DAC 11.0 Operational Amplifier (Opa) Module 11.1 Control Registers 11.1.1 OPACON Register FIGURE 11-1: OPA Module BLOCK Diagram Register 11-1: OPAMP CONTROL REGISTER (OPACON: 11Ch) 11.1.2 CALCON Register FIGURE 11-2: AUTO CALIBRATION MODULE BLOCK DIAGRAM Register 11-2: CALIBRATION CONTROL REGISTER (CALCON: 110h) 11.2 Configuration as OPAMP or Comparator EXAMPLE 11-1: CALIBRATION FOR OPAmp MODE EXAMPLE 11-2: calibration for comparator mode 11.3 Effects of RESET 11.4 OPA Module Performance TABLE 11-1: Registers associated with the opa module 12.0 Comparator Module 12.1 Control Registers 12.1.1 Comparator C1 Control Register TABLE 12-1: Output State versus input conditions FIGURE 12-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM FIGURE 12-2: Comparator C2 Simplified Block Diagram Register 12-1: COMPARATOR C1 CONTROL REGISTER0 (CM1CON0: 119h) 12.1.2 Comparator C2 Control Registers 12.1.2.1 Control Register CM2CON0 Register 12-2: COMPARATOR C2 CONTROL REGISTER0 (CM2CON0: 11Ah) 12.1.2.2 Control Register CM2CON1 Register 12-3: COMPARATOR C2 CONTROL REGISTER1 (CM2CON1: 11Bh) 12.2 Comparator Configuration 12.2.1 EXAMPLE: C2 synchronized to T1CKI FIGURE 12-3: Comparator C2 Configuration With Output Synchronized to T1CKI EXAMPLE 12-1: C2 Configuration Program 12.2.2 EXAMPLE: C1 input to PSMC w/ DAC as reference FIGURE 12-4: Configuration of Comparator C1 with DAC EXAMPLE 12-2: Programming C1 for PSMC Feedback 12.2.3 EXAMPLE: Low power Window Comparator with Interrupt FIGURE 12-5: Window Comparator with Interrupt EXAMPLE 12-3: window comparator 12.3 Effects of RESET TABLE 12-2: Registers associated with the comparator module 13.0 Programmable Switch Mode Controller (PSMC) 13.1 Pulse Width Modulation (PWM) FIGURE 13-1: PSMC Module in Single Output PWM Mode (Simplified Block Diagram) FIGURE 13-2: PSMC Module in Dual Alternating Output PWM Mode (Simplified Block Diagram) TABLE 13-1: PSMC1A output sequence in pwm mode Using C1 Comparator Only TABLE 13-2: PSMC1A output sequence in pwm mode Using C1 and C2 Comparators 13.1.1 Pulse Skip Modulation (PSM) FIGURE 13-3: PSMC Module in Single Output PSM Mode (Simplified Block Diagram) TABLE 13-3: PSMC1A operation in pSm mode Using C1 Comparator Only TABLE 13-4: PSMC1A output sequence in pSm mode Using C1 and C2 Comparators 13.1.2 Single or Dual output 13.1.3 Slope Compensation FIGURE 13-4: SLOPE COMPENSATION (SC) SWITCH OPERATION 13.2 Control Registers 13.2.1 PSMCCON0 Register 13.2.2 PSMCCON1 Register TABLE 13-5: PSMC OUTPUT MODES Register 13-1: PSMC CONTROL REGISTER0 (PSMCCON0: 111h) Register 13-2: PSMC CONTROL REGISTER1 (PSMCCON1: 112h) 13.3 Configuration 13.3.1 EXAMPLE Boost LC switching power supply FIGURE 13-5: EXAMPLE Boost Configuration LC Switching Power Supply EXAMPLE 13-1: PSMC Configuration Example 13.3.2 example BUCK LC SWITCHING POWER SUPPLY EXAMPLE 13-2: example PSMC Configuration for a Buck Mode Switching Power Supply FIGURE 13-6: EXAMPLE BUCK CONFIGURATION LC POWER SUPPLY 13.3.3 EXAMPLE Motor speed control EXAMPLE 13-3: Peripheral Configuration Example FIGURE 13-7: EXAMPLE Brushless D.C. Motor Control 13.4 Effects of SLEEP and RESET TABLE 13-6: Registers Associated with the PSMC 14.0 Special Features Of The Cpu 14.1 Configuration Bits Register 14-1: CONFIGURATION WORD FOR PIC16C781/782 DEVICE (config:2007h) 14.2 Oscillator Configurations 14.2.1 Oscillator Types 14.2.2 LP, XT and HS Modes FIGURE 14-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) TABLE 14-1: Ceramic Resonators TABLE 14-2: Capacitor Selection for Crystal Oscillator 14.2.3 EC Mode FIGURE 14-2: EC OSC Configuration 14.2.4 RC Mode FIGURE 14-3: RC Oscillator Mode 14.2.5 INTRC MODE 14.2.6 Dual Speed Operation for INTRC Mode 14.2.7 CLKOUT 14.3 RESET FIGURE 14-4: Simplified Block Diagram of On-chip Reset Circuit 14.4 Power-on Reset (POR) FIGURE 14-5: External Power-on Reset Circuit (for Slow Vdd Ramp) 14.5 Power-up Timer (PWRT) 14.6 Programmable Brown-out Reset (PBOR) 14.7 Time-out Sequence 14.8 Power Control/Status Register (PCON) TABLE 14-3: Time-out in Various Situations Register 14-2: POWER CONTROL REGISTER (PCON: 8Eh) TABLE 14-4: Status Bits and Their Significance TABLE 14-5: Reset Condition for Special Registers FIGURE 14-6: Time-out Sequence on Power-up (MCLR Tied to Vdd) FIGURE 14-7: Time-out Sequence on Power-up (MCLR not Tied to Vdd) TABLE 14-6: Initialization condition for all registers FIGURE 14-8: Time-out Sequence on Power-up (MCLR not Tied to Vdd) FIGURE 14-9: Slow Vdd Rise Time (MCLR Tied to Vdd) 14.9 Interrupts 14.9.1 INT Interrupt FIGURE 14-10: INTERRUPT LOGIC 14.9.2 TMR0 Interrupt 14.9.3 PortB INTERRUPT-ON-CHANGE (IOCB) 14.10 Context Saving During Interrupts EXAMPLE 14-1: Saving STATUS, W, and PCLATH Registers 14.11 Watchdog Timer (WDT) FIGURE 14-11: Watchdog Timer Block Diagram TABLE 14-7: Summary of Watchdog Timer Registers 14.12 Power-down Mode (SLEEP) 14.12.1 Wake-up from SLEEP 14.12.2 Wake-Up Using Interrupts FIGURE 14-12: Wake-up from Sleep Through Interrupt 15.0 Instruction Set Summary TABLE 15-1: Opcode Field Descriptions FIGURE 15-1: General Format for Instructions TABLE 15-2: PIC16CXXX Instruction Set 15.1 Instruction Descriptions 16.0 Development Support 16.1 MPLAB Integrated Development Environment Software 16.2 MPASM Assembler 16.3 MPLAB C17 and MPLAB C18 C Compilers 16.4 MPLINK Object Linker/ MPLIB Object Librarian 16.5 MPLAB SIM Software Simulator 16.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 16.7 ICEPIC In-Circuit Emulator 16.8 MPLAB ICD In-Circuit Debugger 16.9 PRO MATE II Universal Device Programmer 16.10 PICSTART Plus Entry Level Development Programmer 16.11 PICDEM 1 Low Cost PIC MCU Demonstration Board 16.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board 16.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 16.14 PICDEM 17 Demonstration Board 16.15 KeeLoq Evaluation and Programming Tools TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP 17.0 Electrical Characteristics FIGURE 17-1: PIC16C781/782 Voltage-Frequency Graph, -40°C £ ta £ +85°C FIGURE 17-2: PIC16LC781/782 Voltage-Frequency Graph, -40°C £ ta £ +85°C 17.1 DC Characteristics: Power Supply TABLE 17-1: DC Characteristics: PIC16C781/782, DSTEMP (Industrial) 17.2 DC Characteristics: Input/Output Pins TABLE 17-2: DC Characteristics: PIC16C781/782, DSTEMP (Industrial) 17.3 AC Characteristics: PIC16C781/782 (Industrial) 17.3.1 Timing Parameter Symbology FIGURE 17-3: Load Conditions 17.3.2 Timing Diagrams and Specifications FIGURE 17-4: CLKOUT and I/O Timing TABLE 17-3: CLKOUT and I/O Timing Requirements FIGURE 17-5: External Clock Timing TABLE 17-4: External Clock Timing Requirements TABLE 17-5: Internal RC Oscillator Calibrated Frequencies PIC16C781/782, DSTEMP FIGURE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 17-7: Brown-out Reset Timing TABLE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements FIGURE 17-8: Brown-out Reset Characteristics FIGURE 17-9: Timer0 and Timer1 External Clock Timings TABLE 17-7: Timer0 and Timer1 External Clock Requirements 17.4 Operational Amplifier TABLE 17-8: DC Characteristics: Operational Amplifier (OPA) TABLE 17-9: AC Characteristics: Operational Amplifier (OPA) 17.5 Comparators TABLE 17-10: DC Characteristics: Voltage Comparators C1 AND C2 TABLE 17-11: AC Characteristics: ComparatorS C1 AND C2 17.6 Digital-to-Analog Converter (DAC) TABLE 17-12: DC Characteristics: DIGITAL-TO-ANALOG Converter (DAC) TABLE 17-13: AC Characteristics: DIGITAL-TO-ANALOG Converter (DAC) 17.7 Analog Peripherals Characteristics 17.7.1 Bandgap Voltage 17.7.2 VR Module TABLE 17-15: DC Characteristics: VR 17.7.3 Programmable Low Voltage Detect Module (PLVD) 17.7.4 Programmable Brown-Out Reset Module DC Characteristics: PBOR TABLE 17-18: ADC Converter Characteristics PIC16C781/782 FIGURE 17-11: ADC Conversion Timing TABLE 17-19: ADC Conversion Requirements 18.0 DC and AC Characteristics Graphs and Tables 19.0 PACKAGING INFORMATION 19.1 Package Marking Information A ADC ADC Acquisition Requirements 73 ADC Conversion Clock 72 ADC Minimum Charging Time 73 ADC Operation During SLEEP 75 Analog Signal Multiplexing Diagram 7 Analog-to-digital Converter (ADC) Module 69 Analog-to-Digital Converter Module Assembler B Banking, Data Memory 17 Block Diagrams Boost LC Switching Power Supply 107 BOR BOR. See Brown-out Reset Brown-out Reset (BOR) 117, 125, 126 Buck Configuration LC Power Supply 112 Buck LC Switching Power Supply 110 C C1 Input to PSMC w/DAC as Reference 95 C2 Configuration Program 95 CALCON Register 84 Calculating the Minimum Required Acquisition Time 73 Clock Noise 76 Code Examples Code Protection 117 Comparator C1 Control Register 89 Comparator C2 Configuration With Output Synchronized to T1CKI 95 Comparator C2 Control Registers 92 Comparator C2 Synchronized to T1CKI 95 Comparator Configuration 95 Comparator Module 89 Configuration as OPAMP or Comparator 86 Configuration Bits 117 Configuration of Comparator C1 with DAC 96 Configuring the ADC Module 72 Configuring the Reference Voltages 72 Control Register CM2CON0 92 Control Register T1CON 56 D DAC Configuration 81 DAC Module Data Memory Data Memory Organization 11 DC Characteristics Development Support 141 Device Overview 5 Digital-to-Analog Converter (DAC) Module 79 Direct Addressing 24 E EC Mode 119 Effect of RESET on Core Registers 24 Effects of RESET 52 Electrical Characteristics 147 Errata 3 Examples External Power-on Reset Circuit 122 F Firmware Instructions 133 FSR Register 15 G General Purpose Register File 13 I I/O Port Analog/Digital Mode 25 I/O Ports 25 ICEPIC In-Circuit Emulator 142 ID Locations 117 In-Circuit Serial Programming (ICSP) 117 Indirect Addressing 24 Initialization Condition for All Registers 126 Initializing Timer0 51 Instruction Format 133 Instruction Set 133 INT Interrupt (RB0/INT/AN4/VR). See Interrupt Sources INTCON Register Interrupt Sources 117, 128 Interrupts, Context Saving During 129 Interrupts, Enable Bits Interrupts, Flag Bits K KeeLoq Evaluation and Programming Tools 144 L Low Power Window Comparator with Interrupt 96 Low Voltage Detect Low Voltage Detect Registers 67 Low Voltage Detect Waveforms 65 LP, XT and HS Modes 119 M Master Clear (MCLR) Memory Organization 11 MPLAB C17 and MPLAB C18 C Compilers 141 MPLAB ICD In-Circuit Debugger 143 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 142 MPLAB Integrated Development Environment Software 141 MPLINK Object Linker/MPLIB Object Librarian 142 O OPA Auto Calibration 83 OPA Module OPA Offset Voltage 84 OPCODE Field Descriptions 133 Operational Amplifier (OPA) Module 83 OPTION_REG Register Oscillator Configuration 119 Oscillator, WDT 129 Oscillators OTP Program Memory Read 49 P Package Marking Information 169 Paging, Program Memory 23 PCON Register 123 PICDEM 1 Low Cost PIC MCU Demonstration Board 143 PICDEM 17 Demonstration Board 144 PICDEM 2 Low Cost PIC16CXX Demonstration Board 143 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 144 PICSTART Plus Entry Level Development Programmer 143 Pin Functions Pinout Description PIR1 Register PLVD PLVD Example 67 PMCON1 47 PMDATH and PMDATL Registers 47 PMR Pointer, FSR 23 POR. See Power-on Reset PORTA PORTA and the TRISA Register 26 PORTB PORTB and the TRISB Register 35 PORTB Interrupt-on-Change 35 PORTB Weak Pull-up 35 Postscaler, WDT 52 Power-down Mode. See SLEEP Power-on Reset (POR) 117, 121, 122, 125, 126 Prescaler, Timer0 52 Prescaler, Timer1 PRO MATE II Universal Device Programmer 143 Program 47 Program Counter Program Memory Program Memory Map and Stack Program Memory Organization 11 Program Memory Read (PMR) 47 Program Memory Read Cycle Execution 50 Programmable Brown-out Reset (PBOR) 121, 122 Programmable Low Voltage Detect Module (PLVD) 63 Programmable Switch Mode Controller (PSMC) 99 Programming C1 for PSMC Feedback 96 Programming, Device Instructions 133 PSMC PSMC1A Operation in PSM Mode Using C1 Comparator Only 102 PSMC1A Output Sequence in PSM Mode Using C1 and C2 Comparators 103 PSMC1A Output Sequence in PWM Mode Using C1 and C2 Comparators 101 PSMC1A Output Sequence in PWM Mode Using C1 Comparator Only 100 PSMCCON0 Register 104 PSMCCON1 Register 104 Pulse Skip Modulation (PSM) 102 Pulse Width Modulation (PWM) 99 R Read with Code Protect Set 50 Reading the EPROM Program Memory 49 Registers Registers Associated with VR 61 Registers/Bits Associated with ADC 77 Reset 121 S Setting up the PLVD Module 65 Single or Dual Output 103 SLEEP 117, 121, 131 Slope Compensation 103 Slope Compensation (SC) Switch Operation 103 Software Simulator (MPLAB SIM) 142 Special Features of the CPU 117 Special Function Registers 13 Stack 23 STATUS Register 129 T T1CON Register Tad vs. Device Operating Frequencies 72 Timer0 51 Timer0 Module 51 Timer0 Operation 51 Timer1 Timer1 Incrementing Edge 58 Timer1 Initialization 55 Timer1 Interrupt 59 Timer1 Module Timer/Counter 55 Timer1 Module with Gate Control 55 Timer1 Operation 55 Timer1 Oscillator for the PIC16C781/782 59 Timing Diagrams TRISA, ANSEL, and Control Precedence 26 TRISB, ANSEL, and Control Precedence 36 Typical Low Voltage Detect Application 63 V Voltage Reference Module Voltage Reference Module (VR) 61 W W Register 129 Wake-up from SLEEP 117, 131 Watchdog Timer Watchdog Timer (WDT) 117, 129 Window Comparator with Interrupt 96 WWW, On-Line Support 3 The Microchip Web Site Customer Change Notification Service Customer Support Reader Response PIC16C781/782 Product Identification System Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Indianapolis Toronto Fax: 852-2401-3431 Australia - Sydney China - Beijing China - Shanghai India - Bangalore Korea - Daegu Korea - Seoul Singapore Taiwan - Taipei Fax: 43-7242-2244-393 Denmark - Copenhagen France - Paris Germany - Munich Italy - Milan Spain - Madrid UK - Wokingham Worldwide Sales and Service
PIC16C781/782 8-Bit CMOS Microcontrollers with A/D, D/A, OPAMP, Comparators and PSMC Microcontroller Core Features: Microcontroller Core Features (Continued):
• High performance RISC CPU • Low power, high speed CMOS EPROM • Only 35 single word instructions to learn technology • All single cycle instructions except for program • Fully static design branches which are two cycle • Low power consumption: • Direct, indirect and relative addressing modes - < 2 mA @ 5V, 4 MHz - Operating speed: DC - 20 MHz clock input - < 1 A typical standby current. DC - 200 ns instruction cycle
Pin Diagram Program Data Memory Device Memory PDIP, Windowed CERDIP, SOIC, SSOP X8 X14
RA0/AN0/OPA+ PIC16C781 1K 128 •1 1 20 RB3/AN7/OPA
P
RA1/AN1/OPA- 2 2
I
19 RB2/AN6
C1
RA4/T0CKI PIC16C782 2K 128 3 3 18 RA7/OSC1/CLKIN RA5/MCLR/VPP 4 4
6C
17 RA6/OSC2/CLKOUT/T1CKI 17 • 8-level deep hardware stack VSS 5 5
781
16 VDD AVSS 6 6 15 AVDD 15 • Interrupt capability (up to 8 internal/external RA2/AN2/VREF2 7 7
/78
14 RB7/C2/PSMC1B/T1G RA3/AN3/VREF1 8 8 13 RB6/C1/PSMC1A interrupt sources)
2
RB0/INT/AN4/VR 9 9 12 RB5 • 16 I/O pins: RB1/AN5/VDAC 10 11 RB4 - Individual direction control (13 pins) - Input only (3 pins), low leakage (2 pins)
Peripheral Features:
- Digital/Analog inputs (8 pins) • Programmable PORTB interrupt-on-change (8 pins) • Timer0: 8-bit timer/counter with 8-bit prescaler • Programmable PORTB weak pull-ups (8 pins) • Enhanced Timer1: • Power-on Reset (POR) - 16-bit timer/counter with prescaler • Power-up Timer (PWRT) and - External Gate Input mode Oscillator Start-up Timer (OST) - Option to use OSC1 and OSC2 in LP mode • Watchdog Timer (WDT) with a software enabled as Timer1 oscillator, if INTRC oscillator mode option and its own on-chip RC oscillator for selected reliable operation • Analog-to-Digital Converter (ADC):
• Programmable Brown-out Reset (BOR) - 8-bit resolution • Programmable Low Voltage Detection (LVD) - Programmable 8-channel input • Internal/external MCLR - Internal voltages available for self- • Programmable code protection diagnostics • Power saving SLEEP mode • Digital-to-Analog Converter (DAC): • Selectable oscillator options: - 8-bit resolution HS, XT, LP, EC, RC, INTRC (4 MHz/37 kHz) - Reference from AVDD, VREF1, or VR module • In-Circuit Serial Programming™ (ISCP™) - Output configurable to VDAC pin, Compara- • Program Memory Read (PMR) capability tors, and ADC reference • Four user programmable ID locations • Operational Amplifier module (OPA): • Wide operating voltage range: - Firmware initiated input offset voltage Auto Calibration module - 2.5V to 5.5V for commercial and industrial temperature ranges - Low leakage inputs - Extended temperature range available - Programmable Gain Bandwidth Product (GBWP) 2001-2013 Microchip Technology Inc.
Preliminary
DS41171B-page 1 Document Outline Microcontroller Core Features: Microcontroller Core Features (Continued): Peripheral Features: Peripheral Features (Continued): Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: PIC16C781 BLOCK DIAGRAM FIGURE 1-2: PIC16C782 BLOCK DIAGRAM FIGURE 1-3: Analog Signal Multiplexing Diagram 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: PIC16C781 PROGRAM MEMORY MAP AND STACK FIGURE 2-2: PIC16C782 PROGRAM MEMORY MAP AND STACK 2.2 Data Memory Organization FIGURE 2-3: REGISTER FILE MAP 2.2.1 General Purpose register file 2.2.2 Special Function Registers TABLE 2-1: PIC16C781/782 SPECIAL FUNCTION REGISTER SUMMARY 2.3 STATUS Register Register 2-1: Status REGISTER (STATUS: 03h, 83h, 103h, 183h) 2.4 OPTION_REG Register Register 2-2: OPTION Register (OPTION_REG: 81h, 181h) 2.5 INTCON Register Register 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh) 2.6 PIE1 Register Register 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER (PIE1: 8Ch) 2.7 PIR1 Register Register 2-5: PERIPHERAL INTERRUPT REGISTER (PIR1 0Ch) 2.8 PCON Register Register 2-6: POWER CONTROL REGISTER (PCON: 8Eh) 2.9 PCL and PCLATH 2.9.1 Program Memory Paging 2.10 Stack 2.11 INDF EXAMPLE 2-1: How to Clear RAM Using Indirect Addressing FIGURE 2-4: Loading of PC in Different Situations FIGURE 2-5: Direct/Indirect Addressing 2.12 Effect of RESET on Core Registers TABLE 2-2: Effect of reset on core registers 3.0 I/o Ports 3.1 I/O Port Analog/Digital Mode Register 3-1: Analog select register (ansel: 9Dh) 3.2 PORTA and the TRISA Register EXAMPLE 3-1: Initializing PortA 3.2.1 TRISA, ANSEL, and control precedence FIGURE 3-1: Block Diagram of RA0/AN0/OPA+ PIN FIGURE 3-2: Block Diagram of RA1/AN1/OPA- PIN FIGURE 3-3: Block Diagram of RA2/AN2/Vref2 PIN FIGURE 3-4: Block Diagram of RA3/AN3/Vref1 PIN FIGURE 3-5: Block Diagram of RA4/T0CKI PIN FIGURE 3-6: Block Diagram of RA5/MCLR/Vpp PIN FIGURE 3-7: Block Diagram of RA6/OSC2/CLKOUT/T1CKI PIN FIGURE 3-8: Block Diagram of RA7/OSC1/CLKIN PIN TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA 3.3 PORTB and the TRISB Register EXAMPLE 3-2: INITIALIZING PORTB 3.3.1 PortB Weak Pull-up 3.3.2 PortB Interrupt-On-Change Register 3-2: Weak Pull-Up PORTB Register (WPUB: 95h) Register 3-3: Interrupt-on-Change PORTB Register (IOCB: 96h) 3.3.3 TRISB, ANSEL, and control precedence FIGURE 3-9: Block Diagram of RB0/INT/AN4/Vr PIN FIGURE 3-10: Block Diagram of RB1/AN5/Vdac PIN FIGURE 3-11: Block Diagram of RB2/AN6 PIN FIGURE 3-12: Block Diagram of RB3/AN7/OPA PIN FIGURE 3-13: Block Diagram of RB4 PIN FIGURE 3-14: Block Diagram of RB5 pin FIGURE 3-15: Block Diagram of RB6/C1/PSMC1A PIN FIGURE 3-16: Block Diagram of RB7/C2/PSMC1B/T1G PIN TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB 4.0 Program Memory Read (Pmr) 4.1 PMCON1 Register 4.2 PMDATH and PMDATL Registers Register 4-1: program memory read Control Register 1 (pmCON1: 18Ch) Register 4-2: PROGRAM MEMORY DATA HIGH (PMDATH: 10Eh) Register 4-3: PROGRAM MEMORY DATA LOW (PMDATL: 10Ch) Register 4-4: PROGRAM MEMORY ADDRESS HIGH (PMADRH: 10Fh) Register 4-5: PROGRAM MEMORY ADDRESS LOW (PMADRL: 10Dh) 4.3 Reading the EPROM Program Memory EXAMPLE 4-1: OTP PROGRAM MEMORY READ 4.4 Program Memory Read With Code Protect Set TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PMR FIGURE 4-1: Program Memory Read Cycle Execution 5.0 Timer0 Module 5.1 Timer0 Operation EXAMPLE 5-1: INITIALIZING TIMER0 FIGURE 5-1: Timer0 Block Diagram 5.2 Prescaler 5.2.1 Switching Prescaler Assignment 5.3 Timer0 Interrupt 5.4 Effects of RESET FIGURE 5-2: Block Diagram of the Timer0/WDT Prescaler TABLE 5-1: Registers Associated with Timer0 6.0 Timer1 Module with gate Control 6.1 Timer1 Operation EXAMPLE 6-1: Timer1 Initialization 6.2 Control Register T1CON Register 6-1: TIMER1 CONTROL REGISTER (T1CON: ADDRESS 10h) FIGURE 6-1: Timer1 Incrementing Edge FIGURE 6-2: Timer1 ON THE PIC16C781/782 Block Diagram 6.3 Timer1 Oscillator for the PIC16C781/782 6.4 Timer1 Interrupt 6.5 Effects of RESET TABLE 6-1: summary of REGISTERS ASSOCIATED WITH TIMER1 7.0 Voltage Reference Module (Vr) 7.1 Effects of RESET 7.2 Registers Associated with Vr Register 7-1: Voltage Reference Control Register (REFCON: 9Bh) TABLE 7-1: Summary of Registers Associated with Vr 8.0 programmable LOW Voltage Detect MODULE (PLVD) FIGURE 8-1: Typical Low Voltage Detect Application 8.1 Control Register 8.2 Operation FIGURE 8-2: Low Voltage Detect Block Diagram 8.2.1 Setting Up the PLVD Module FIGURE 8-3: Low Voltage Detect waveforms Register 8-1: programmable LOW VOLTAGE DETECT Register (LVDCON: 9Ch) EXAMPLE 8-1: PLVD EXAMPLE 8.3 Operation During SLEEP 8.4 Effects of a RESET 8.5 Low Voltage Detect Registers TABLE 8-1: Summary of Registers Associated with LOW voltage detect 9.0 Analog-to-digital Converter (Adc) Module FIGURE 9-1: ADC Module Block Diagram 9.1 Control Registers 9.1.1 ADCON0 Register Register 9-1: ADC Control register 0 (adcon0: 1fh) 9.1.2 ADCON1 Register 9.1.3 ADRES REGISTER Register 9-2: ADC RESULT REGISTER (ADRES: 1Eh) Register 9-3: ADC control register 1 (adcon1: 9Fh) 9.2 Configuring the ADC Module 9.2.1 CONFIGURING ANALOG PORT PINS 9.2.2 CONFIGURING THE REFERENCE VOLTAGES 9.2.3 SELECTING THE ADC CONVERSION CLOCK TABLE 9-1: TAD vs. DEVICE OPERATING FREQUENCIES: PIC16C781/782 9.2.4 Initiating a Conversion 9.3 ADC Acquisition Requirements EQUATION 9-1: ADC MINIMUM CHARGING TIME EXAMPLE 9-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME FIGURE 9-2: Analog Input Model 9.4 ADC Configuration and Conversion EXAMPLE 9-2: ADC Conversion 9.4.1 Faster Conversion/Lower Resolution Trade-off 9.5 ADC Operation During SLEEP 9.6 ADC Accuracy/Error 9.6.1 Clock Noise 9.7 Effects of a RESET 9.8 Connection Considerations 9.9 Transfer Function 9.10 References FIGURE 9-3: ADC Transfer Function FIGURE 9-4: Flow chart of ADC Operation TABLE 9-2: Registers/Bits Associated with ADC, PIC16C781/782 10.0 Digital-to-analog Converter (DAC) Module 10.1 Control Registers Register 10-1: DIGITAL-TO-ANALOG CONVERTER CONTROL REGISTER0 (DACON0: 11Fh) Register 10-2: DIGITAL-TO-ANALOG CONVERTER REGISTER (DAC: 11Eh) 10.2 Control Register FIGURE 10-1: DAC Converter Block Diagram 10.3 DAC Configuration EXAMPLE 10-1: DAC configuration 10.4 Effects of RESET 10.5 DAC Module Accuracy/Error FIGURE 10-2: DAC TRANSFER FUNCTION TABLE 10-1: Registers/Bits Associated with DAC 11.0 Operational Amplifier (Opa) Module 11.1 Control Registers 11.1.1 OPACON Register FIGURE 11-1: OPA Module BLOCK Diagram Register 11-1: OPAMP CONTROL REGISTER (OPACON: 11Ch) 11.1.2 CALCON Register FIGURE 11-2: AUTO CALIBRATION MODULE BLOCK DIAGRAM Register 11-2: CALIBRATION CONTROL REGISTER (CALCON: 110h) 11.2 Configuration as OPAMP or Comparator EXAMPLE 11-1: CALIBRATION FOR OPAmp MODE EXAMPLE 11-2: calibration for comparator mode 11.3 Effects of RESET 11.4 OPA Module Performance TABLE 11-1: Registers associated with the opa module 12.0 Comparator Module 12.1 Control Registers 12.1.1 Comparator C1 Control Register TABLE 12-1: Output State versus input conditions FIGURE 12-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM FIGURE 12-2: Comparator C2 Simplified Block Diagram Register 12-1: COMPARATOR C1 CONTROL REGISTER0 (CM1CON0: 119h) 12.1.2 Comparator C2 Control Registers 12.1.2.1 Control Register CM2CON0 Register 12-2: COMPARATOR C2 CONTROL REGISTER0 (CM2CON0: 11Ah) 12.1.2.2 Control Register CM2CON1 Register 12-3: COMPARATOR C2 CONTROL REGISTER1 (CM2CON1: 11Bh) 12.2 Comparator Configuration 12.2.1 EXAMPLE: C2 synchronized to T1CKI FIGURE 12-3: Comparator C2 Configuration With Output Synchronized to T1CKI EXAMPLE 12-1: C2 Configuration Program 12.2.2 EXAMPLE: C1 input to PSMC w/ DAC as reference FIGURE 12-4: Configuration of Comparator C1 with DAC EXAMPLE 12-2: Programming C1 for PSMC Feedback 12.2.3 EXAMPLE: Low power Window Comparator with Interrupt FIGURE 12-5: Window Comparator with Interrupt EXAMPLE 12-3: window comparator 12.3 Effects of RESET TABLE 12-2: Registers associated with the comparator module 13.0 Programmable Switch Mode Controller (PSMC) 13.1 Pulse Width Modulation (PWM) FIGURE 13-1: PSMC Module in Single Output PWM Mode (Simplified Block Diagram) FIGURE 13-2: PSMC Module in Dual Alternating Output PWM Mode (Simplified Block Diagram) TABLE 13-1: PSMC1A output sequence in pwm mode Using C1 Comparator Only TABLE 13-2: PSMC1A output sequence in pwm mode Using C1 and C2 Comparators 13.1.1 Pulse Skip Modulation (PSM) FIGURE 13-3: PSMC Module in Single Output PSM Mode (Simplified Block Diagram) TABLE 13-3: PSMC1A operation in pSm mode Using C1 Comparator Only TABLE 13-4: PSMC1A output sequence in pSm mode Using C1 and C2 Comparators 13.1.2 Single or Dual output 13.1.3 Slope Compensation FIGURE 13-4: SLOPE COMPENSATION (SC) SWITCH OPERATION 13.2 Control Registers 13.2.1 PSMCCON0 Register 13.2.2 PSMCCON1 Register TABLE 13-5: PSMC OUTPUT MODES Register 13-1: PSMC CONTROL REGISTER0 (PSMCCON0: 111h) Register 13-2: PSMC CONTROL REGISTER1 (PSMCCON1: 112h) 13.3 Configuration 13.3.1 EXAMPLE Boost LC switching power supply FIGURE 13-5: EXAMPLE Boost Configuration LC Switching Power Supply EXAMPLE 13-1: PSMC Configuration Example 13.3.2 example BUCK LC SWITCHING POWER SUPPLY EXAMPLE 13-2: example PSMC Configuration for a Buck Mode Switching Power Supply FIGURE 13-6: EXAMPLE BUCK CONFIGURATION LC POWER SUPPLY 13.3.3 EXAMPLE Motor speed control EXAMPLE 13-3: Peripheral Configuration Example FIGURE 13-7: EXAMPLE Brushless D.C. Motor Control 13.4 Effects of SLEEP and RESET TABLE 13-6: Registers Associated with the PSMC 14.0 Special Features Of The Cpu 14.1 Configuration Bits Register 14-1: CONFIGURATION WORD FOR PIC16C781/782 DEVICE (config:2007h) 14.2 Oscillator Configurations 14.2.1 Oscillator Types 14.2.2 LP, XT and HS Modes FIGURE 14-1: Crystal/Ceramic Resonator Operation (HS, XT or LP OSC Configuration) TABLE 14-1: Ceramic Resonators TABLE 14-2: Capacitor Selection for Crystal Oscillator 14.2.3 EC Mode FIGURE 14-2: EC OSC Configuration 14.2.4 RC Mode FIGURE 14-3: RC Oscillator Mode 14.2.5 INTRC MODE 14.2.6 Dual Speed Operation for INTRC Mode 14.2.7 CLKOUT 14.3 RESET FIGURE 14-4: Simplified Block Diagram of On-chip Reset Circuit 14.4 Power-on Reset (POR) FIGURE 14-5: External Power-on Reset Circuit (for Slow Vdd Ramp) 14.5 Power-up Timer (PWRT) 14.6 Programmable Brown-out Reset (PBOR) 14.7 Time-out Sequence 14.8 Power Control/Status Register (PCON) TABLE 14-3: Time-out in Various Situations Register 14-2: POWER CONTROL REGISTER (PCON: 8Eh) TABLE 14-4: Status Bits and Their Significance TABLE 14-5: Reset Condition for Special Registers FIGURE 14-6: Time-out Sequence on Power-up (MCLR Tied to Vdd) FIGURE 14-7: Time-out Sequence on Power-up (MCLR not Tied to Vdd) TABLE 14-6: Initialization condition for all registers FIGURE 14-8: Time-out Sequence on Power-up (MCLR not Tied to Vdd) FIGURE 14-9: Slow Vdd Rise Time (MCLR Tied to Vdd) 14.9 Interrupts 14.9.1 INT Interrupt FIGURE 14-10: INTERRUPT LOGIC 14.9.2 TMR0 Interrupt 14.9.3 PortB INTERRUPT-ON-CHANGE (IOCB) 14.10 Context Saving During Interrupts EXAMPLE 14-1: Saving STATUS, W, and PCLATH Registers 14.11 Watchdog Timer (WDT) FIGURE 14-11: Watchdog Timer Block Diagram TABLE 14-7: Summary of Watchdog Timer Registers 14.12 Power-down Mode (SLEEP) 14.12.1 Wake-up from SLEEP 14.12.2 Wake-Up Using Interrupts FIGURE 14-12: Wake-up from Sleep Through Interrupt 15.0 Instruction Set Summary TABLE 15-1: Opcode Field Descriptions FIGURE 15-1: General Format for Instructions TABLE 15-2: PIC16CXXX Instruction Set 15.1 Instruction Descriptions 16.0 Development Support 16.1 MPLAB Integrated Development Environment Software 16.2 MPASM Assembler 16.3 MPLAB C17 and MPLAB C18 C Compilers 16.4 MPLINK Object Linker/ MPLIB Object Librarian 16.5 MPLAB SIM Software Simulator 16.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 16.7 ICEPIC In-Circuit Emulator 16.8 MPLAB ICD In-Circuit Debugger 16.9 PRO MATE II Universal Device Programmer 16.10 PICSTART Plus Entry Level Development Programmer 16.11 PICDEM 1 Low Cost PIC MCU Demonstration Board 16.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board 16.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 16.14 PICDEM 17 Demonstration Board 16.15 KeeLoq Evaluation and Programming Tools TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP 17.0 Electrical Characteristics FIGURE 17-1: PIC16C781/782 Voltage-Frequency Graph, -40°C £ ta £ +85°C FIGURE 17-2: PIC16LC781/782 Voltage-Frequency Graph, -40°C £ ta £ +85°C 17.1 DC Characteristics: Power Supply TABLE 17-1: DC Characteristics: PIC16C781/782, DSTEMP (Industrial) 17.2 DC Characteristics: Input/Output Pins TABLE 17-2: DC Characteristics: PIC16C781/782, DSTEMP (Industrial) 17.3 AC Characteristics: PIC16C781/782 (Industrial) 17.3.1 Timing Parameter Symbology FIGURE 17-3: Load Conditions 17.3.2 Timing Diagrams and Specifications FIGURE 17-4: CLKOUT and I/O Timing TABLE 17-3: CLKOUT and I/O Timing Requirements FIGURE 17-5: External Clock Timing TABLE 17-4: External Clock Timing Requirements TABLE 17-5: Internal RC Oscillator Calibrated Frequencies PIC16C781/782, DSTEMP FIGURE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 17-7: Brown-out Reset Timing TABLE 17-6: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Reset Requirements FIGURE 17-8: Brown-out Reset Characteristics FIGURE 17-9: Timer0 and Timer1 External Clock Timings TABLE 17-7: Timer0 and Timer1 External Clock Requirements 17.4 Operational Amplifier TABLE 17-8: DC Characteristics: Operational Amplifier (OPA) TABLE 17-9: AC Characteristics: Operational Amplifier (OPA) 17.5 Comparators TABLE 17-10: DC Characteristics: Voltage Comparators C1 AND C2 TABLE 17-11: AC Characteristics: ComparatorS C1 AND C2 17.6 Digital-to-Analog Converter (DAC) TABLE 17-12: DC Characteristics: DIGITAL-TO-ANALOG Converter (DAC) TABLE 17-13: AC Characteristics: DIGITAL-TO-ANALOG Converter (DAC) 17.7 Analog Peripherals Characteristics 17.7.1 Bandgap Voltage 17.7.2 VR Module TABLE 17-15: DC Characteristics: VR 17.7.3 Programmable Low Voltage Detect Module (PLVD) 17.7.4 Programmable Brown-Out Reset Module DC Characteristics: PBOR TABLE 17-18: ADC Converter Characteristics PIC16C781/782 FIGURE 17-11: ADC Conversion Timing TABLE 17-19: ADC Conversion Requirements 18.0 DC and AC Characteristics Graphs and Tables 19.0 PACKAGING INFORMATION 19.1 Package Marking Information A ADC ADC Acquisition Requirements 73 ADC Conversion Clock 72 ADC Minimum Charging Time 73 ADC Operation During SLEEP 75 Analog Signal Multiplexing Diagram 7 Analog-to-digital Converter (ADC) Module 69 Analog-to-Digital Converter Module Assembler B Banking, Data Memory 17 Block Diagrams Boost LC Switching Power Supply 107 BOR BOR. See Brown-out Reset Brown-out Reset (BOR) 117, 125, 126 Buck Configuration LC Power Supply 112 Buck LC Switching Power Supply 110 C C1 Input to PSMC w/DAC as Reference 95 C2 Configuration Program 95 CALCON Register 84 Calculating the Minimum Required Acquisition Time 73 Clock Noise 76 Code Examples Code Protection 117 Comparator C1 Control Register 89 Comparator C2 Configuration With Output Synchronized to T1CKI 95 Comparator C2 Control Registers 92 Comparator C2 Synchronized to T1CKI 95 Comparator Configuration 95 Comparator Module 89 Configuration as OPAMP or Comparator 86 Configuration Bits 117 Configuration of Comparator C1 with DAC 96 Configuring the ADC Module 72 Configuring the Reference Voltages 72 Control Register CM2CON0 92 Control Register T1CON 56 D DAC Configuration 81 DAC Module Data Memory Data Memory Organization 11 DC Characteristics Development Support 141 Device Overview 5 Digital-to-Analog Converter (DAC) Module 79 Direct Addressing 24 E EC Mode 119 Effect of RESET on Core Registers 24 Effects of RESET 52 Electrical Characteristics 147 Errata 3 Examples External Power-on Reset Circuit 122 F Firmware Instructions 133 FSR Register 15 G General Purpose Register File 13 I I/O Port Analog/Digital Mode 25 I/O Ports 25 ICEPIC In-Circuit Emulator 142 ID Locations 117 In-Circuit Serial Programming (ICSP) 117 Indirect Addressing 24 Initialization Condition for All Registers 126 Initializing Timer0 51 Instruction Format 133 Instruction Set 133 INT Interrupt (RB0/INT/AN4/VR). See Interrupt Sources INTCON Register Interrupt Sources 117, 128 Interrupts, Context Saving During 129 Interrupts, Enable Bits Interrupts, Flag Bits K KeeLoq Evaluation and Programming Tools 144 L Low Power Window Comparator with Interrupt 96 Low Voltage Detect Low Voltage Detect Registers 67 Low Voltage Detect Waveforms 65 LP, XT and HS Modes 119 M Master Clear (MCLR) Memory Organization 11 MPLAB C17 and MPLAB C18 C Compilers 141 MPLAB ICD In-Circuit Debugger 143 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE 142 MPLAB Integrated Development Environment Software 141 MPLINK Object Linker/MPLIB Object Librarian 142 O OPA Auto Calibration 83 OPA Module OPA Offset Voltage 84 OPCODE Field Descriptions 133 Operational Amplifier (OPA) Module 83 OPTION_REG Register Oscillator Configuration 119 Oscillator, WDT 129 Oscillators OTP Program Memory Read 49 P Package Marking Information 169 Paging, Program Memory 23 PCON Register 123 PICDEM 1 Low Cost PIC MCU Demonstration Board 143 PICDEM 17 Demonstration Board 144 PICDEM 2 Low Cost PIC16CXX Demonstration Board 143 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 144 PICSTART Plus Entry Level Development Programmer 143 Pin Functions Pinout Description PIR1 Register PLVD PLVD Example 67 PMCON1 47 PMDATH and PMDATL Registers 47 PMR Pointer, FSR 23 POR. See Power-on Reset PORTA PORTA and the TRISA Register 26 PORTB PORTB and the TRISB Register 35 PORTB Interrupt-on-Change 35 PORTB Weak Pull-up 35 Postscaler, WDT 52 Power-down Mode. See SLEEP Power-on Reset (POR) 117, 121, 122, 125, 126 Prescaler, Timer0 52 Prescaler, Timer1 PRO MATE II Universal Device Programmer 143 Program 47 Program Counter Program Memory Program Memory Map and Stack Program Memory Organization 11 Program Memory Read (PMR) 47 Program Memory Read Cycle Execution 50 Programmable Brown-out Reset (PBOR) 121, 122 Programmable Low Voltage Detect Module (PLVD) 63 Programmable Switch Mode Controller (PSMC) 99 Programming C1 for PSMC Feedback 96 Programming, Device Instructions 133 PSMC PSMC1A Operation in PSM Mode Using C1 Comparator Only 102 PSMC1A Output Sequence in PSM Mode Using C1 and C2 Comparators 103 PSMC1A Output Sequence in PWM Mode Using C1 and C2 Comparators 101 PSMC1A Output Sequence in PWM Mode Using C1 Comparator Only 100 PSMCCON0 Register 104 PSMCCON1 Register 104 Pulse Skip Modulation (PSM) 102 Pulse Width Modulation (PWM) 99 R Read with Code Protect Set 50 Reading the EPROM Program Memory 49 Registers Registers Associated with VR 61 Registers/Bits Associated with ADC 77 Reset 121 S Setting up the PLVD Module 65 Single or Dual Output 103 SLEEP 117, 121, 131 Slope Compensation 103 Slope Compensation (SC) Switch Operation 103 Software Simulator (MPLAB SIM) 142 Special Features of the CPU 117 Special Function Registers 13 Stack 23 STATUS Register 129 T T1CON Register Tad vs. Device Operating Frequencies 72 Timer0 51 Timer0 Module 51 Timer0 Operation 51 Timer1 Timer1 Incrementing Edge 58 Timer1 Initialization 55 Timer1 Interrupt 59 Timer1 Module Timer/Counter 55 Timer1 Module with Gate Control 55 Timer1 Operation 55 Timer1 Oscillator for the PIC16C781/782 59 Timing Diagrams TRISA, ANSEL, and Control Precedence 26 TRISB, ANSEL, and Control Precedence 36 Typical Low Voltage Detect Application 63 V Voltage Reference Module Voltage Reference Module (VR) 61 W W Register 129 Wake-up from SLEEP 117, 131 Watchdog Timer Watchdog Timer (WDT) 117, 129 Window Comparator with Interrupt 96 WWW, On-Line Support 3 The Microchip Web Site Customer Change Notification Service Customer Support Reader Response PIC16C781/782 Product Identification System Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Indianapolis Toronto Fax: 852-2401-3431 Australia - Sydney China - Beijing China - Shanghai India - Bangalore Korea - Daegu Korea - Seoul Singapore Taiwan - Taipei Fax: 43-7242-2244-393 Denmark - Copenhagen France - Paris Germany - Munich Italy - Milan Spain - Madrid UK - Wokingham Worldwide Sales and Service
