Datasheet AH4930 (Diodes) - 5
| Manufacturer | Diodes |
| Description | 3D Magnetic Linear Hall Sensor with I2C Interface |
| Pages / Page | 23 / 5 — AH4930. Electrical Characteristics. Timing Requirements for I2C:. 400kHz … |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
AH4930. Electrical Characteristics. Timing Requirements for I2C:. 400kHz (Fast Mode). 1000kHz (Fast Mode+). Symbol. Parameter. Unit
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AH4930 Electrical Characteristics
(VDD = 3.3V @TA = +25°C, unless otherwise specified.) (continued)
Timing Requirements for I2C: 400kHz (Fast Mode) 1000kHz (Fast Mode+) Symbol Parameter Unit Min Typ Max Min Typ Max
fSCL I2C clock frequency — — 400 — — 1000 kHz tL Clock low time 1.3 — — 0.5 — — µs tH Clock high time 0.6 — — 0.4 — — µs Hold time for a (repeated) START tSTA 0.6 — — 0.4 — — µs condition tSTOP Setup time for STOP condition 0.6 — — 0.4 — — µs tSU Data setup time 0.1 — — 0.1 — — µs tHOLD Data hold time 0 — — 0 — — µs tRISE Rise time of SDA and SCL (Note 9) — — 0.5 — — 0.5 µs tFALL Fall time of SDA and SCL (Note 9) — — 0.3 — 0.25 0.3 µs Bus free time between a STOP and a tWAIT 0.6 — — 0.4 — — µs START condition Note: 9. Dependent on used R-C combination. For applications, total capacitive load should be < 200pF.
t t t t RISE FALL FALL tRISE STOP tWAIT t t STA tSU tHOLD H tL SDA SCL STOP START R/W BIT R/W BIT R/W BIT Figure 1. I2C Timing Parameters
AH4930 5 of 23 January 2025 Document number: DS46768 Rev. 1 - 2
www.diodes.com
© 2025 Copyright Diodes Incorporated. All Rights Reserved.
(VDD = 3.3V @TA = +25°C, unless otherwise specified.) (continued)
Timing Requirements for I2C: 400kHz (Fast Mode) 1000kHz (Fast Mode+) Symbol Parameter Unit Min Typ Max Min Typ Max
fSCL I2C clock frequency — — 400 — — 1000 kHz tL Clock low time 1.3 — — 0.5 — — µs tH Clock high time 0.6 — — 0.4 — — µs Hold time for a (repeated) START tSTA 0.6 — — 0.4 — — µs condition tSTOP Setup time for STOP condition 0.6 — — 0.4 — — µs tSU Data setup time 0.1 — — 0.1 — — µs tHOLD Data hold time 0 — — 0 — — µs tRISE Rise time of SDA and SCL (Note 9) — — 0.5 — — 0.5 µs tFALL Fall time of SDA and SCL (Note 9) — — 0.3 — 0.25 0.3 µs Bus free time between a STOP and a tWAIT 0.6 — — 0.4 — — µs START condition Note: 9. Dependent on used R-C combination. For applications, total capacitive load should be < 200pF.
t t t t RISE FALL FALL tRISE STOP tWAIT t t STA tSU tHOLD H tL SDA SCL STOP START R/W BIT R/W BIT R/W BIT Figure 1. I2C Timing Parameters
AH4930 5 of 23 January 2025 Document number: DS46768 Rev. 1 - 2
www.diodes.com
© 2025 Copyright Diodes Incorporated. All Rights Reserved.
