Datasheet HCPL-2300 (Broadcom) - 10

Applications
The HCPL-2300/HCPL-0300 optocoupler has the unique The recommended shunt drive technique for TTL/LSTTL/ combination of low 0.5 mA LED operating drive current at a CMOS of Figure 12 provides for optimal speed perfor- 5 MBd speed performance. Low power supply current mance, no leakage current path through the LED, and re- requirement of 10 mA maximum at 5.25 V and the abil- duced common mode influences associated with series ity to provide isolation between logic systems fulfills switching of a “floating” LED. Alternate series drive tech- numerous applications ranging from logic level transla- niques with either an active CMOS inverter or an open tions, line receiver and party line receiver applications, collector TTL/LSTTL inverter are illustrated in Figures 13 microprocessor I/O port isolation, etc. The open col lector and 14 respectively. Open collector leakage current of output allows for wired-OR arrangement. Specific inter- 250 µA has been compensated by the 3.16 KΩ resistor face circuits are illustrated in Figures 12-16, and 18 with (Figure 14) at the expense of twice the operating forward correspond ing component values, perform ance data current. and recom mended layout in Figures 17 and 19. An application of the HCPL-2300/HCPL-0300 as an un- For -40°C to 85°C operating temperature range, a mid- balanced line receiver for use in long line twisted wire range LED forward current (I ) of 0.625 mA is recommend- pair communication links is shown in Figure 15. Low F ed in order to prevent overdriving the integrated circuit LED I and V allow longer line length, higher speed F F detector due to increased LED efficiency at temperatures and multiple stations on the line in comparison to between 0°C and -40°C. For narrower temperature range higher I , V optocouplers. Greater speed performance F F of 0°C to 85°C, a suggested operating LED current of along with nearly infinite common mode immu- 0.75 mA is recommended for the mid-range operating nity are achieved via the balanced split phase circuit point and for minimal propagation delay skew. of Figure 16. Basic balanced differential line re- A peaking capacitance of 20 pF in parallel with the cur- ceiver can be accomplished with one HCPL- rent limiting resistor for the LED shortens t by approxi- 2300/HCPL-0300 in Figure 16, but with a typical PHL mately 33% and t by 13%. Maintain ing LED forward 400 V/µs common mode immunity. Data rate versus dis- PLH voltage (V ) below 0.8 V will guarantee that the HCPL- tance for both the above unbalanced and balanced line F 2300/HCPL-0300 output is off. receiver applications are com pared in Figure 17. The RS- 232-C interface circuit of Figure 18 provides guaranteed minimum common mode immunity of 100 V/µs while maintaining the 2:1 dynamic range of I . F
HCPL-0300/ HCPL-2300 Figure 10. Test circuit for common mode transient immunity and typical waveforms.
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