Datasheet LTC7878 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 70V Parallelable 4-Switch Buck-Boost Controller with Inductor DCR Current Sensing |
| Pages / Page | 30 / 8 — PIN FUNCTIONS (QFN/LFCSP) BG1, BG2 (Pins 1, 8/Pins 1, 12):. SW2, SW1 … |
| File Format / Size | PDF / 2.4 Mb |
| Document Language | English |
PIN FUNCTIONS (QFN/LFCSP) BG1, BG2 (Pins 1, 8/Pins 1, 12):. SW2, SW1 (Pins 11, 30/Pins 16, 45):. IN (Pin 2/Pin 4):
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PIN FUNCTIONS (QFN/LFCSP) BG1, BG2 (Pins 1, 8/Pins 1, 12):
Bottom Gate Driver
SW2, SW1 (Pins 11, 30/Pins 16, 45):
Switch Node Outputs. These pins drive the gates of the bottom Connections. Normally connect to the inductor termi- N-Channel MOSFETs between PGND and DRVCC. nals. SW1 swings from a Schottky diode voltage drop
V
below ground up to VIN and SW2 swings from a Schottky
IN (Pin 2/Pin 4):
Main IC Supply. Power input to the internal LDO connect to DRV diode voltage drop below ground up to VOUT. A bootstrap CC. Bypass this pin to PGND with a capacitor (0.1μF to 1μF) close to the pin. capacitor (0.1μF to 1μF) should be placed from each SW pin to the corresponding BOOST pin as close as possible.
DRVCC (Pin 3/Pin 7):
Gate Driver Current Supply LDO Output. The voltage on this pin is regulated to 7V from
PGOOD (Pin 12/Pin 19):
Power Good Inductor Output for either V the Regulated Output Voltage. Open-drain logic out that is IN or EXTVCC during normal operation. Bypass this pin to PGND with a minimum of 4.7μF low ESR tantalum pulled down to ground when the regulated output voltage or ceramic capacitor. exceeds ±10% regulation window, after the internal 30µs power bad mask timer expires.
EXTVCC (Pin 4/Pin 8):
External Power Input to an Internal LDO Connected to DRV
SS (Pin 13/Pin 20):
Soft-Start Input. The voltage ramp CC. When the voltage on this pin is greater 8V and lower than the V rate at this pin sets the output voltage ramp rate of the IN pin voltage, this LDO bypasses the internal LDO powered from V regulated voltage. A capacitor to ground accomplishes IN. Bypass this pin to PGND with a capacitor (0.1μF to 1μF) close soft-start. This pin has a 2.5µA pull-up current. to the pin.
ITHB (Pin 14/Pin 21):
Fast Transient Current Control
INTV
Threshold. Optional transient response improvement
CC (Pin 5/Pin 9):
Internal 5V Regulator Output. The control circuits are powered from this voltage. Bypass this configure pin based on the ITH pin voltage and operation pin to SGND with a minimum of 4.7µF low ESR tantalum mode. A resistor from ITHB pin to ITH pin may improve or ceramic capacitor. the transient response in buck mode. If no use, short ITHB pin and ITH pin together. See Applications Information
RUN (Pin 6/Pin 10):
Enable Control Input. A voltage above section for details. Do not float this pin. 1.22V turns on the IC. There is a 2µA pull-up current on this pin. Once the RUN pin rises above the 1.22V thresh-
ITH (Pin 15/Pin 22):
Current Control Threshold and Error old, the pull-up increases to 6µA. Amplifier Compensation Point. The current compara- tor’s threshold varies with the ITH control voltage. The
PGND (Pin 7/Pin 11):
Power Ground Pin. Connect this Compensation network is from ITH pin to SGND. pin closely to the sources of bottom N-channel MOSFETs and negative terminal of V
VFB (Pin 16/Pin 25):
Output Voltage Sensing Error IN, DRVCC, EXTVCC bypass capacitors. Amplifier Noninverting Input. This pin receives the remotely sensed feedback voltage from external resistor
TG2, TG1 (Pins 9, 32/Pins 14, 47):
Top Gate Driver divider across the output voltage. Outputs. These are the outputs of floating drivers with a voltage swing equal to DRV
MODE/ILIM (Pin 17/Pin 26):
FCM/Pulse-Skipping Mode CC superimposed on the switching nodes voltages. and Inductor Current Limit Program Pin. Tying this pin to GND or INTVCC enables forced continuous mode oper-
BOOST2, BOOST1 (Pins 10, 31/Pins 15, 46):
ation, otherwise the controller works in the pulse-skip- Bootstrapped Supplies to the Top Side Floating Drivers. ping mode. Tying this pin to a voltage lower than half of Capacitors are connected between the BOOST and SW INTVCC enables the low current limit, higher than half of pins and Schottky diodes are tied between the BOOST INTVCC enables the high current limit. See Applications and DRVCC pins. Voltage swing at the BOOST1 pin is from Information section for details. DRVCC to (VIN + DRVCC). Voltage swing at the BOOST2 pin is from DRVCC to (VOUT + DRVCC). Rev. C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS (QFN/LFCSP) BG1, BG2 (Pins 1, 8/Pins 1, 12):
Bottom Gate Driver
SW2, SW1 (Pins 11, 30/Pins 16, 45):
Switch Node Outputs. These pins drive the gates of the bottom Connections. Normally connect to the inductor termi- N-Channel MOSFETs between PGND and DRVCC. nals. SW1 swings from a Schottky diode voltage drop
V
below ground up to VIN and SW2 swings from a Schottky
IN (Pin 2/Pin 4):
Main IC Supply. Power input to the internal LDO connect to DRV diode voltage drop below ground up to VOUT. A bootstrap CC. Bypass this pin to PGND with a capacitor (0.1μF to 1μF) close to the pin. capacitor (0.1μF to 1μF) should be placed from each SW pin to the corresponding BOOST pin as close as possible.
DRVCC (Pin 3/Pin 7):
Gate Driver Current Supply LDO Output. The voltage on this pin is regulated to 7V from
PGOOD (Pin 12/Pin 19):
Power Good Inductor Output for either V the Regulated Output Voltage. Open-drain logic out that is IN or EXTVCC during normal operation. Bypass this pin to PGND with a minimum of 4.7μF low ESR tantalum pulled down to ground when the regulated output voltage or ceramic capacitor. exceeds ±10% regulation window, after the internal 30µs power bad mask timer expires.
EXTVCC (Pin 4/Pin 8):
External Power Input to an Internal LDO Connected to DRV
SS (Pin 13/Pin 20):
Soft-Start Input. The voltage ramp CC. When the voltage on this pin is greater 8V and lower than the V rate at this pin sets the output voltage ramp rate of the IN pin voltage, this LDO bypasses the internal LDO powered from V regulated voltage. A capacitor to ground accomplishes IN. Bypass this pin to PGND with a capacitor (0.1μF to 1μF) close soft-start. This pin has a 2.5µA pull-up current. to the pin.
ITHB (Pin 14/Pin 21):
Fast Transient Current Control
INTV
Threshold. Optional transient response improvement
CC (Pin 5/Pin 9):
Internal 5V Regulator Output. The control circuits are powered from this voltage. Bypass this configure pin based on the ITH pin voltage and operation pin to SGND with a minimum of 4.7µF low ESR tantalum mode. A resistor from ITHB pin to ITH pin may improve or ceramic capacitor. the transient response in buck mode. If no use, short ITHB pin and ITH pin together. See Applications Information
RUN (Pin 6/Pin 10):
Enable Control Input. A voltage above section for details. Do not float this pin. 1.22V turns on the IC. There is a 2µA pull-up current on this pin. Once the RUN pin rises above the 1.22V thresh-
ITH (Pin 15/Pin 22):
Current Control Threshold and Error old, the pull-up increases to 6µA. Amplifier Compensation Point. The current compara- tor’s threshold varies with the ITH control voltage. The
PGND (Pin 7/Pin 11):
Power Ground Pin. Connect this Compensation network is from ITH pin to SGND. pin closely to the sources of bottom N-channel MOSFETs and negative terminal of V
VFB (Pin 16/Pin 25):
Output Voltage Sensing Error IN, DRVCC, EXTVCC bypass capacitors. Amplifier Noninverting Input. This pin receives the remotely sensed feedback voltage from external resistor
TG2, TG1 (Pins 9, 32/Pins 14, 47):
Top Gate Driver divider across the output voltage. Outputs. These are the outputs of floating drivers with a voltage swing equal to DRV
MODE/ILIM (Pin 17/Pin 26):
FCM/Pulse-Skipping Mode CC superimposed on the switching nodes voltages. and Inductor Current Limit Program Pin. Tying this pin to GND or INTVCC enables forced continuous mode oper-
BOOST2, BOOST1 (Pins 10, 31/Pins 15, 46):
ation, otherwise the controller works in the pulse-skip- Bootstrapped Supplies to the Top Side Floating Drivers. ping mode. Tying this pin to a voltage lower than half of Capacitors are connected between the BOOST and SW INTVCC enables the low current limit, higher than half of pins and Schottky diodes are tied between the BOOST INTVCC enables the high current limit. See Applications and DRVCC pins. Voltage swing at the BOOST1 pin is from Information section for details. DRVCC to (VIN + DRVCC). Voltage swing at the BOOST2 pin is from DRVCC to (VOUT + DRVCC). Rev. C 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts