Datasheet CH32X033, CH32X035 (Nanjing Qinheng Microelectronics) - 6
| Manufacturer | Nanjing Qinheng Microelectronics |
| Description | USB+Type-C PD MCU |
| Pages / Page | 47 / 6 — 1.4 Functional Description. 1.4.1 RISC-V4C Processor. 1.4.2 Programmable … |
| Revision | 2.3 |
| File Format / Size | PDF / 815 Kb |
| Document Language | English |
1.4 Functional Description. 1.4.1 RISC-V4C Processor. 1.4.2 Programmable Protocol I/O Controller (PIOC). 1.4.3 On-chip Memory
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CH32X035 Datasheet https://wch-ic.com
1.4 Functional Description 1.4.1 RISC-V4C Processor
RISC-V4C supports the IMAC subset of the RISC-V instruction set. The processor is managed internally in a modular fashion and contains units such as a programmable fast interrupt controller (PFIC), memory protection, branch prediction mode and extended instruction support. Externally multiple buses are connected to external unit modules, enabling interaction between external function modules and the core. The processor with its minimal instruction set, multiple operating modes, and modular custom extensions can be flexibly applied to different scenarios of microcontroller design, such as small area low-power embedded scenarios, high performance application operating system scenarios, etc. Support machine and user privileged modes Programmable Fast Interrupt Controller (PFIC) Multi-level hardware interrupt stack 2-wire serial debug interface (SDI) Standard memory protection design Static or dynamic branch prediction, efficient jumping, conflict detection mechanisms Custom extension instructions
1.4.2 Programmable Protocol I/O Controller (PIOC)
Programmable protocol I/O controller is based on a single clock cycle dedicated compact instruction set RISC core running at system mains frequency with 2K instruction program ROM and 49 SFR registers and PWM timer/counter, supporting protocol control of 2 I/O pins. Multiplex 4K bytes of system SRAM as a 2K word capacity program ROM, supporting program pause and dynamic loading. Provide 33 bytes of 1 register each in bidirectional and unidirectional mode, providing 6 levels of independent stacking. Support 1- and 2-wire interfaces with multiple protocol specifications by dynamically loading different protocol programs.
1.4.3 On-chip Memory
Built-in 20K bytes SRAM area for data storage and data loss after power down. Among them, 4K can be used for PIOC. Built-in 62K bytes program flash memory storage area (Code FLASH), i.e. user area, for user's application program and constant data storage. Built-in 3328 bytes system storage area (System FLASH), i.e. BOOT area, for system boot program storage, built- in bootstrap loading program. This region can be used for the user area together with the aforementioned 62K-byte region via the WCH-LinkUtility tool. For details, refer to the relevant EVT. 256-byte system non-volatile configuration information storage area, used for vendor configuration word storage, factory-cured, user cannot be modified. 256-byte user-defined information storage area for user-selected word storage.
1.4.4 Power Supply Scheme
VDD = 2 ~ 5.5V: supplies power to the I/O pins and internal regulator. (When using the ADC or PD, VDD should be no less than 2.5V.) V2.3 4 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules
1.4 Functional Description 1.4.1 RISC-V4C Processor
RISC-V4C supports the IMAC subset of the RISC-V instruction set. The processor is managed internally in a modular fashion and contains units such as a programmable fast interrupt controller (PFIC), memory protection, branch prediction mode and extended instruction support. Externally multiple buses are connected to external unit modules, enabling interaction between external function modules and the core. The processor with its minimal instruction set, multiple operating modes, and modular custom extensions can be flexibly applied to different scenarios of microcontroller design, such as small area low-power embedded scenarios, high performance application operating system scenarios, etc. Support machine and user privileged modes Programmable Fast Interrupt Controller (PFIC) Multi-level hardware interrupt stack 2-wire serial debug interface (SDI) Standard memory protection design Static or dynamic branch prediction, efficient jumping, conflict detection mechanisms Custom extension instructions
1.4.2 Programmable Protocol I/O Controller (PIOC)
Programmable protocol I/O controller is based on a single clock cycle dedicated compact instruction set RISC core running at system mains frequency with 2K instruction program ROM and 49 SFR registers and PWM timer/counter, supporting protocol control of 2 I/O pins. Multiplex 4K bytes of system SRAM as a 2K word capacity program ROM, supporting program pause and dynamic loading. Provide 33 bytes of 1 register each in bidirectional and unidirectional mode, providing 6 levels of independent stacking. Support 1- and 2-wire interfaces with multiple protocol specifications by dynamically loading different protocol programs.
1.4.3 On-chip Memory
Built-in 20K bytes SRAM area for data storage and data loss after power down. Among them, 4K can be used for PIOC. Built-in 62K bytes program flash memory storage area (Code FLASH), i.e. user area, for user's application program and constant data storage. Built-in 3328 bytes system storage area (System FLASH), i.e. BOOT area, for system boot program storage, built- in bootstrap loading program. This region can be used for the user area together with the aforementioned 62K-byte region via the WCH-LinkUtility tool. For details, refer to the relevant EVT. 256-byte system non-volatile configuration information storage area, used for vendor configuration word storage, factory-cured, user cannot be modified. 256-byte user-defined information storage area for user-selected word storage.
1.4.4 Power Supply Scheme
VDD = 2 ~ 5.5V: supplies power to the I/O pins and internal regulator. (When using the ADC or PD, VDD should be no less than 2.5V.) V2.3 4 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules