Datasheet CH32X033, CH32X035 (Nanjing Qinheng Microelectronics) - 8

CH32X035 Datasheet https://wch-ic.com Vector table support address or instruction mode Interrupt nesting depth can be configured up to 2 levels Support interrupt tail linking function
1.4.9 External Interrupt/Event Controller (EXTI)
The external interrupt/event controller contains a total of 28 edge detectors for generating interrupt/event requests. Each interrupt line can be configured independently of its trigger event (rising or falling edge or double edge) and can be individually masked; a pending register maintains the status of all interrupt requests. Up to 60 general purpose I/O ports are optionally connected to 24 external interrupt lines.
1.4.10 General DMA Controller
The system has a built-in general purpose DMA controller that manages 8 channels to flexibly handle high-speed data transfers between memory to memory, peripheral to memory and memory to peripheral, supporting the ring buffer approach. Each channel has dedicated hardware DMA request logic to support one or more peripheral access requests to memory, with configurable access priority, transfer length, source and destination addresses for transfers, etc. DMA is used for the main peripherals including: General-purpose/advanced-control timers TIMx, ADC, USART, I2C, SPI. USB and USB PD have additional dedicated independent DMA channels. Note: DMA and CPU access to system SRAM after arbiter arbitration.
1.4.11 Clock and Boot
The system clock source HSI is turned on by default, and the internal 48MHz RC oscillator 6 division is used as the default CPU clock when no clock is configured or after a reset. For low power modes where the clock is turned off, the system will first turn on the internal RC oscillator upon wake-up. If the clock interrupt is enabled, the software can receive the corresponding interrupt.
1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey)
The chip has a built-in 12-bit analog/digital converter (ADC) providing up to 14 external channels and 1 internal channel sample, with programmable channel sample times for single, continuous, sweep or intermittent conversion. The provision of an analogue watchdog function allows very accurate monitoring of one or more selected channels for monitoring channel signal voltages. Supports external event-triggered transitions, with trigger sources including internal signals from the on-chip timer and external pins. Supports the use of DMA operation. ADC internal channels are internal reference supply voltage sampling channels. Touch key capacitance detection unit, providing up to 14 detection channels, multiplexes the external channels of the ADC module. The detection results are converted to output results by the ADC module, and the touch key status is identified by the touch detection algorithm subroutine library or by user software. Note: ADC's channel 3, channel 7, channel 11, and channel 15 functions are not applicable to products whose lot number ends with 0 as the fifth-to-last digit. V2.3 6 Document Outline Overview Features Chapter 1 Specification Information 1.1 System Structure 1.2 Memory Map 1.3 Clock Tree 1.4 Functional Description 1.4.1 RISC-V4C Processor 1.4.2 Programmable Protocol I/O Controller (PIOC) 1.4.3 On-chip Memory 1.4.4 Power Supply Scheme 1.4.5 Power Supply Monitor 1.4.6 System Voltage Regulator LDO 1.4.7 Low-power Mode 1.4.8 Programmable Fast Interrupt Controller (PFIC) 1.4.9 External Interrupt/Event Controller (EXTI) 1.4.10 General DMA Controller 1.4.11 Clock and Boot 1.4.12 Analog-to-digital Converter (ADC) and Touchkey Capacitance Detection (TKey) 1.4.13 Timer and Watchdog 1.4.14 Universal Synchronous/Asynchronous Receiver Transmitter (USART) 1.4.15 Serial Peripheral Interface (SPI) 1.4.16 I2C Bus 1.4.17 Universal Serial Bus USB2.0 Full-speed Host/Device Controller (USBFS) 1.4.18 USB PD and Type-C Controller (USB PD) 1.4.19 General-purpose Input and Output (GPIO) 1.4.20 Operational Amplifier/Comparator (OPA) 1.4.21 Voltage Comparator (CMP) 1.4.22 2-wire SDI Serial Debug Interface Chapter 2 Pinouts and Pin Definition 2.1 Pinouts 2.2 Pin Description 2.3 Pin Alternate Functions Chapter 3 Electrical Characteristics 3.1 Test Conditions 3.2 Absolute Maximum Ratings 3.3 Electrical Characteristics 3.3.1 Operating Conditions 3.3.2 Built-in Reset and Power Control Module Characteristics 3.3.3 Built-in Reference Voltage 3.3.4 Supply Current Characteristics 3.3.5 Internal Clock Source Characteristics 3.3.6 Wakeup Time from Low-power Mode 3.3.7 Memory Characteristics 3.3.8 I/O Port Characteristics 3.3.9 RST Pin Characteristics 3.3.10 USB PD Interface Characteristics 3.3.11 TIM Timer Characteristics 3.3.12 I2C Interface Characteristics 3.3.13 SPI Interface Characteristics 3.3.14 USART Characteristics 3.3.15 USB Interface Characteristics 3.3.16 12-bit ADC Characteristics 3.3.17 OPA Characteristics 3.3.18 CMP Characteristics Chapter 4 Package and Ordering Information Packages 4.1 LQFP64M Package 4.2 LQFP48 Package 4.3 QFN28 Package 4.4 QSOP28 Package 4.5 QFN20 Package 4.6 TSSOP20 Package 4.7 QFN12 Package Series Product Naming Rules