Reference Manual CH32X035 (Nanjing Qinheng Microelectronics) - 8
| Manufacturer | Nanjing Qinheng Microelectronics |
| Description | USB+Type-C PD MCU |
| Pages / Page | 261 / 8 — VDD. VPOR. 20mV Hysteresis. VPDR. Reset lag time. tRSTTEMPO. Reset … |
| Revision | 1.9 |
| File Format / Size | PDF / 2.6 Mb |
| Document Language | English |
VDD. VPOR. 20mV Hysteresis. VPDR. Reset lag time. tRSTTEMPO. Reset signal. 2.2.2 Programmable Voltage Detector. Approx. PVD. 20mV
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CH32X035 Reference Manual https://wch-ic.com Figure 2-2 Schematic diagram of the operation of POR and PDR
VDD VPOR 20mV Hysteresis VPDR Reset lag time tRSTTEMPO Reset signal 0 1 0 2.2.2 Programmable Voltage Detector
The programmable voltage detector, PVD, is mainly used to monitor the change of the main power supply of the system and compare it with the threshold voltage set by PLS[1:0] of the power control register PWR_CTLR, and with the external interrupt register (EXTI) setting, it can generate relevant interrupts to notify the system in time for pre-power down operations such as data saving. The specific configuration is as follows. 1) Set the PLS[1:0] field of the PWR_CTLR register and select the voltage threshold to be monitored. 2) Optional interrupt handling. the PVD function is internally connected to the rising/falling edge trigger setting of line 26 of the EXTI module, turning on this interrupt (Configuring EXTI) will generate a PVD interrupt when VDD drops below the PVD threshold or rises above the PVD threshold. 3) Read the PVD0 bit of the PWR_CSR status register can obtain the current system mains power in relation to the PLS[1:0] setting threshold and perform the corresponding soft processing. Figure 2-3 Schematic diagram of PVD operation
VDD Approx. PVD 20mV Threshold value hysteresis PVD output 1 0 1
V1.9 6 Document Outline Overview Chapter 1 Memory and Bus Architecture 1.1 Bus Architecture 1.2 Memory Map 1.2.1 Memory Allocation Chapter 2 Power Control (PWR) 2.1 Overview 2.2 Power Management 2.2.1 Power-on Reset and Power-down Reset 2.2.2 Programmable Voltage Detector 2.3 Low-power Modes 2.3.1 Low-power Configuration Options 2.3.2 Sleep Mode 2.3.3 Stop Mode 2.3.4 Standby Mode 2.3.5 Auto-wakeup (AWU) 2.4 Register Description 2.4.1 Power Control Register (PWR_CTLR) 2.4.2 Power Control/Status Register (PWR_CSR) Chapter 3 Reset and Clock Control (RCC) 3.1 Main Features 3.2 Reset 3.2.1 Power Reset 3.2.2 System Reset 3.3 Clock 3.3.1 System Clock Structure 3.3.2 High-speed Clock (HSI) 3.3.3 Bus/Peripheral Clock 3.3.3.1 System Clock (SYSCLK) 3.3.3.2 HB Bus Peripheral Clock (HCLK) 3.3.3.3 Independent Watchdog Clock 3.3.3.4 Microcontroller Clock Output (MCO) 3.4 Register Description 3.4.1 Clock Control Register (RCC_CTLR) 3.4.2 Clock Configuration Register0 (RCC_CFGR0) 3.4.3 PB2 Peripheral Reset Register (RCC_APB2PRSTR) 3.4.4 PB1 Peripheral Reset Register (RCC_APB1PRSTR) 3.4.5 HB Peripheral Clock Enable Register (RCC_AHBPCENR) 3.4.6 PB2 Peripheral Clock Enable Register (RCC_APB2PCENR) 3.4.7 PB1 Peripheral Clock Enable Register (RCC_APB1PCENR) 3.4.8 Control/Status Register (RCC_RSTSCKR) 3.4.9 HB Peripheral Reset Register (RCC_AHBRSTR) Chapter 4 Auto-wakeup (AWU) 4.1 Main Features 4.2 Function Description 4.3 Register Description 4.3.1 AWU Control/Status Register (AWU_CSR) 4.3.2 AWU Wake-up Window Register (AWU_WR) 4.3.3 AWU Prescaler Register (AWU_PSC) Chapter 5 Independent Watchdog (IWDG) 5.1 Main Features 5.2 Function Description 5.2.1 Principle and Application 5.2.2 Debug Mode 5.3 Register Description 5.3.1 Control Register (IWDG_CTLR) 5.3.2 Prescaler Register (IWDG_PSCR) 5.3.3 Reload Register (IWDG_RLDR) 5.3.4 Status Register (IWDG_STATR) Chapter 6 Window Watchdog (WWDG) 6.1 Main Features 6.2 Function Description 6.2.1 Principle and Application 6.2.2 Debug Mode 6.3 Register Description 6.3.1 Control Register (WWDG_CTLR) 6.3.2 Configuration Register (WWDG_CFGR) 6.3.3 Status Register (WWDG_STATR) Chapter 7 Interrupt and Events (PFIC) 7.1 Main Features 7.1.1 PFIC 7.2 System Timer 7.3 Vector Table of Interrupts and Exceptions 7.4 External Interrupt and Event Controller (EXTI) 7.4.1 Overview 7.4.2 Wake-up Event 7.4.3 Description 7.4.4 External Event Mapping 7.5 Register Description 7.5.1 EXTI Registers 7.5.1.1 Interrupt Enable Register (EXTI_INTENR) 7.5.1.2 Event Enable Register (EXTI_EVENR) 7.5.1.3 Rising Edge Trigger Enable Register (EXTI_RTENR) 7.5.1.4 Falling Edge Trigger Enable Register (EXTI_FTENR) 7.5.1.5 Software Interrupt Event Register (EXTI_SWIEVR) 7.5.1.6 Interrupt Flag Register (EXTI_INTFR) 7.5.2 PFIC Registers 7.5.2.1 PFIC Interrupt Enable Status Register 1 (PFIC_ISR1) 7.5.2.2 PFIC Interrupt Enable Status Register 2 (PFIC_ISR2) 7.5.2.3 PFIC Interrupt Enable Status Register 3 (PFIC_ISR3) 7.5.2.4 PFIC Interrupt Enable Status Register 4 (PFIC_ISR4) 7.5.2.5 PFIC Interrupt Pending Status Register 1 (PFIC_IPR1) 7.5.2.6 PFIC Interrupt Pending Status Register 2 (PFIC_IPR2) 7.5.2.7 PFIC Interrupt Pending Status Register 3 (PFIC_IPR3) 7.5.2.8 PFIC Interrupt Pending Status Register 4 (PFIC_IPR4) 7.5.2.9 PFIC Interrupt Priority Threshold Configuration Register (PFIC_ITHRESDR) 7.5.2.10 PFIC Interrupt Configuration Register (PFIC_CFGR) 7.5.2.11 PFIC Interrupt Global Status Register (PFIC_GISR) 7.5.2.12 PFIC VTF Interrupt ID Configuration Register (PFIC_VTFIDR) 7.5.2.13 PFIC VTF Interrupt 0 Address Register (PFIC_VTFADDRR0) 7.5.2.14 PFIC VTF Interrupt 1 Address Register (PFIC_VTFADDRR1) 7.5.2.15 PFIC VTF Interrupt 2 Address Register (PFIC_VTFADDRR2) 7.5.2.16 PFIC VTF Interrupt 3 Address Register (PFIC_VTFADDRR3) 7.5.2.17 PFIC Interrupt Enable Setting Register 1 (PFIC_IENR1) 7.5.2.18 PFIC Interrupt Enable Setting Register 2 (PFIC_IENR2) 7.5.2.19 PFIC Interrupt Enable Setting Register 3 (PFIC_IENR3) 7.5.2.20 PFIC Interrupt Enable Setting Register 4 (PFIC_IENR4) 7.5.2.21 PFIC Interrupt Enable Clear Register 1 (PFIC_IRER1) 7.5.2.22 PFIC Interrupt Enable Clear Register 2 (PFIC_IRER2) 7.5.2.23 PFIC Interrupt Enable Clear Register 3 (PFIC_IRER3) 7.5.2.24 PFIC Interrupt Enable Clear Register 4 (PFIC_IRER4) 7.5.2.25 PFIC Interrupt Pending Setting Register 1 (PFIC_IPSR1) 7.5.2.26 PFIC Interrupt Pending Setting Register 2 (PFIC_IPSR2) 7.5.2.27 PFIC Interrupt Pending Setting Register 3 (PFIC_IPSR3) 7.5.2.28 PFIC Interrupt Pending Setting Register 4 (PFIC_IPSR4) 7.5.2.29 PFIC Interrupt Pending Clear Register 1 (PFIC_IPRR1) 7.5.2.30 PFIC Interrupt Pending Clear Register 2 (PFIC_IPRR2) 7.5.2.31 PFIC Interrupt Pending Clear Register 3 (PFIC_IPRR3) 7.5.2.32 PFIC Interrupt Pending Clear Register 4 (PFIC_IPRR4) 7.5.2.33 PFIC Interrupt Activation Status Register 1 (PFIC_IACTR1) 7.5.2.34 PFIC Interrupt Activation Status Register 2 (PFIC_IACTR2) 7.5.2.35 PFIC Interrupt Activation Status Register 3 (PFIC_IACTR3) 7.5.2.36 PFIC Interrupt Activation Status Register 4 (PFIC_IACTR4) 7.5.2.37 PFIC Interrupt Priority Configuration Register (PFIC_IPRIORx) (x=0-63) 7.5.2.38 PFIC System Control Register (PFIC_SCTLR) 7.5.3 Dedicated CSR Registers 7.5.3.1 Interrupt System Control Register (INTSYSCR) 7.5.3.2 Exception Entry Base Address Register (MTVEC) 7.5.4 Physical Memory Protection Unit (PMP) 7.5.4.1 PMP Configuration Register (PMPCFG0) 7.5.4.2 PMP Address 0 Register (PMPADDR0) 7.5.4.3 PMP Address 1 Register (PMPADDR1) 7.5.4.4 PMP Address 2 Register (PMPADDR2) 7.5.4.5 PMP Address 3 Register (PMPADDR3) 7.5.5 STK Register Description 7.5.5.1 System Count Control Register (STK_CTLR) 7.5.5.2 System Count Status Register (STK_SR) 7.5.5.3 System Counter Low Register (STK_CNTL) 7.5.5.4 System Counter High Register (STK_CNTH) 7.5.5.5 Counting Comparison Low Register (STK_CMPLR) 7.5.5.6 Counting Comparison High Register (STK_CMPHR) Chapter 8 GPIO and Alternate Function (GPIO/AFIO) 8.1 Main Features 8.2 Function Description 8.2.1 Overview 8.2.2 GPIO Initialization Function 8.2.3 External Interrupts 8.2.4 Alternate Functions 8.2.5 Locking Mechanism 8.2.6 Input Configuration 8.2.7 Output Configuration 8.2.8 Alternate Function Configuration 8.2.9 Analog Input Configuration 8.2.10 GPIO Settings for Peripherals 8.2.11 BC Function Configuration 8.3 Register Description 8.3.1 GPIO Register Description 8.3.1.1 Port Configuration Register Low [7:0] (GPIOx_CFGLR) (x=A/B/C) 8.3.1.2 Port Configuration Register High [15:8] (GPIOx_CFGHR) (x=A/B/C) 8.3.1.3 Port Input Data Register (GPIOx_INDR) (x=A/B/C) 8.3.1.4 Port Output Data Register (GPIOx_OUTDR) (x=A/B/C) 8.3.1.5 Port Reset/Set Register (GPIOx_BSHR) (x=A/B/C) 8.3.1.6 Port Reset Register (GPIOx_BCR) (x=A/B/C) 8.3.1.7 Port Lock Configuration Register (GPIOx_LCKR) (x=A/B/C) 8.3.1.8 GPIO Configuration Register Expansion (16-23) Bits (GPIOx_CFGXR) (x=A/B/C) 8.3.1.9 Port Set/Reset Register High (16-23) Bits (GPIOx_BSXR) (x=A/B/C) 8.3.2 AFIO Register Description 8.3.2.1 Remap Register 1 (AFIO_PCFR1) 8.3.2.2 External Interrupt Configuration Register 1 (AFIO_EXTICR1) 8.3.2.3 External Interrupt Configuration Register 2 (AFIO_EXTICR2) 8.3.2.4 Control Register (AFIO_CTLR) Chapter 9 Direct Memory Access Control (DMA) 9.1 Main Features 9.2 Function Description 9.2.1 DMA Channel Processing 9.2.2 Programmable Total Data Transfer Size/Data Bit Width/Alignment 9.2.3 DMA Request Mapping 9.3 Register Description 9.3.1 DMA Interrupt Status Register (DMA_INTFR) 9.3.2 DMA Interrupt Flag Clear Register (DMA_INTFCR) 9.3.3 DMA Channel x Configuration Register (DMA_CFGRx)(x=1/2/3/4/5/6/7/8) 9.3.4 DMA Channel x Number of Data Register (DMA_CNTRx) (x=1/2/3/4/5/6/7/8) 9.3.5 DMA Channel x Peripheral Address Register (DMA_PADDRx) (x=1/2/3/4/5/6/7/8) 9.3.6 DMA Channel x Memory Address Register (DMA_MADDRx) (x=1/2/3/4/5/6/7/8) Chapter 10 Analog-to-digital Converter (ADC) 10.1 Main Features 10.2 Functional Description 10.2.1 Module Structure 10.2.2 ADC Configuration 10.2.3 External Trigger Source 10.2.4 Conversion Mode 10.2.5 Analog Watchdog 10.3 Register Description 10.3.1 ADC Status Register (ADC_STATR) 10.3.2 ADC Control Register 1 (ADC_CTLR1) 10.3.3 ADC Control Register 2 (ADC_CTLR2) 10.3.4 ADC Sample Time Configuration Register 1 (ADC_SAMPTR1) 10.3.5 ADC Sample Time Configuration Register 2 (ADC_SAMPTR2) 10.3.6 ADC Injected Channel Data Offset Register x (ADC_IOFRx) (x=1/2/3/4) 10.3.7 ADC Watchdog High Threshold Register (ADC_WDHTR) 10.3.8 ADC Watchdog Low Threshold Register (ADC_WDLTR) 10.3.9 ADC Regular Sequence Register 1(ADC_RSQR1) 10.3.10 ADC Regular Sequence Register 2 (ADC_RSQR2) 10.3.11 ADC Regular Sequence Register 3 (ADC_RSQR3) 10.3.12 ADC Injected Sequence Register (ADC_ISQR) 10.3.13 ADC Injected Data Register (ADC_IDATARx) (x=1/2/3/4) 10.3.14 ADC Regular Data Register (ADC_RDATAR) 10.3.15 ADC Control Register 3 (ADC_CTLR3) 10.3.16 ADC Watchdog 1 Threshold Register (ADC_WDTR1) 10.3.17 ADC Watchdog 2 Threshold Register (ADC_WDTR2) 10.3.18 ADC Watchdog 3 Threshold Register (ADC_WDTR3) Chapter 11 Touch Key Detection (TKEY) 11.1 TKEY Functional Description 11.2 TKEY Operation Procedures 11.3 TKEY Register Description 11.3.1 TKEYx Charge Sample Time Register 1 (TKEYx_CHARGE1) (x=1) 11.3.2 TKEYx Charge Sample Time Register 2 (TKEYx_CHARGE2) (x=1) 11.3.3 TKEYx Charge Time Offset Register (TKEYx_CHGOFFSET) (x=1) 11.3.4 TKEYx Start and Discharge Time Register (TKEYx_ACT_DCG) (x=1) 11.3.5 TKEYx Data Register (TKEYx_DR) (x=1) Chapter 12 Advanced-control Timer (ADTM) 12.1 Main Features 12.2 Principle and Structure 12.2.1 Overview 12.2.2 Clock Input 12.2.2.1 Internal Clock Source (CK_INT) 12.2.2.2 External Clock Source Mode1 12.2.2.3 External Clock Source Mode2 12.2.2.4 Encoder Mode 12.2.3 Counters and Peripherals 12.2.4 Compare/Capture Channels and Peripherals 12.3 Function and Implementation 12.3.1 Counter Mode 12.3.2 Input Capture Mode 12.3.3 Compare Output Mode 12.3.4 Forced Output Mode 12.3.5 PWM Input Mode 12.3.6 PWM Output Mode 12.3.7 Complementary Outputs and Dead-time Insertion 12.3.8 Brake Signal 12.3.9 One-pulse Mode 12.3.10 Encoder Mode 12.3.11 Synchronization of TIMx Timers and External Triggers 12.3.12 Timer Synchronization Mode 12.3.13 Debug Mode 12.4 Register Description 12.4.1 Control Register 1 (TIMx_CTLR1) (x=1/2) 12.4.2 Control Register 2 (TIMx_CTLR2) (x=1/2) 12.4.3 Slave Mode Control Register (TIMx_SMCFGR) (x=1/2) 12.4.4 DMA/Interrupt Enable Register (TIMx_DMAINTENR) (x=1/2) 12.4.5 Interrupt Status Register (TIMx_INTFR) (x=1/2) 12.4.6 Event Generation Register (TIMx_SWEVGR) (x=1/2) 12.4.7 Compare/Capture Control Register 1 (TIMx_CHCTLR1) (x=1/2) 12.4.8 Compare/Capture Control Register 2 (TIMx_CHCTLR2) (x=1/2) 12.4.9 Compare/Capture Enable Register 2 (TIMx_CCER) (x=1/2) 12.4.10 Counter for Advanced-control Timer (TIMx_CNT) (x=1/2) 12.4.11 Counting Clock Prescaler (TIMx_PSC) (x=1/2) 12.4.12 Auto-reload Value Register (TIMx_ATRLR) (x=1/2) 12.4.13 Repeat Count Value Register (TIMx_RPTCR) (x=1/2) 12.4.14 Compare/Capture Register 1 (TIMx_CH1CVR) (x=1/2) 12.4.15 Compare/Capture Register 2 (TIMx_CH2CVR) (x=1/2) 12.4.16 Compare/Capture Register 3 (TIMx_CH3CVR) (x=1/2) 12.4.17 Compare/Capture Register 4 (TIMx_CH4CVR) (x=1/2) 12.4.18 Brake and Dead-time Register (TIMx_BDTR) (x=1/2) 12.4.19 DMA Control Register (TIMx_DMACFGR) (x=1/2) 12.4.20 DMA Address Register for Continuous Mode (TIMx_DMAADR) (x=1/2) 12.4.21 SPEC Register (TIMx_SPEC) (x=1/2) Chapter 13 General-Purpose Timer (GPTM) 13.1 Main Features 13.2 Principle and Structure 13.2.1 Overview 13.2.2 Differences between General-Purpose Timer and Advanced-Control Timer 13.2.3 Clock Input 13.2.3.1 Internal Clock Source (CK_INT) 13.2.3.2 External Clock Source Mode 1 13.2.4 Counters and Peripherals 13.2.5 Compare/capture Channels 13.3 Function and Implementation 13.3.1 Counter Mode 13.3.2 Input Capture Mode 13.3.3 Compare Output Mode 13.3.4 Forced Output Mode 13.3.5 PWM Input Mode 13.3.6 PWM Output Mode 13.3.7 Single Pulse Mode 13.3.8 Synchronization of TIMx Timers and External Triggers 13.3.10 Debug mode 13.4 Register Description 13.4.1 Control Register 1 (TIM3_CTLR1) 13.4.2 Slave Mode Control Register (TIM3_SMCFGR) 13.4.3 DMA/Interrupt Enable Register (TIM3_DMAINTENR) 13.4.4 Interrupt Status Register (TIM3_INTFR) 13.4.5 Event Generation Register (TIM3_SWEVGR) 13.4.6 Compare/Capture Control Register 1 (TIM3_CHCTLR1) 13.4.7 Compare/Capture Enable Register (TIM3_CCER) 13.4.8 Counter for General-purpose Timer (TIM3_CNT) 13.4.9 Counting Clock Prescaler (TIM3_PSC) 13.4.10 Auto-reload Value Register (TIM3_ATRLR) 13.4.11 Compare/Capture Register 1 (TIM3_CH1CVR) 13.4.12 Compare/Capture Register 2 (TIM3_CH2CVR) 13.4.13 SPEC Register (TIM3_SPEC) Chapter 14 Universal Synchronous Asynchronous Receiver Transmitter (USART) 14.1 Main Features 14.2 Overview 14.3 Baud Rate Generator 14.4 Synchronous Mode 14.5 1-Wire Half-Duplex Mode 14.6 Smart Card 14.7 IrDA 14.8 DMA 14.9 Interrupts 14.10 Register Description 14.10.1 USART Status Register (USARTx_STATR) (x=1/2/3/4) 14.10.2 USART Data Register (USARTx_DATAR) (x=1/2/3/4) 14.10.3 USART Baud Rate Register (USARTx_BRR) (x=1/2/3/4) 14.10.4 USART Control Register 1 (USARTx_CTLR1) (x=1/2/3/4) 14.10.5 USART Control Register 2 (USARTx_CTLR2) (x=1/2/3/4) 14.10.6 USART Control Register 3 (USARTx_CTLR3) (x=1/2/3/4) 14.10.7 USART Guard Time and Prescaler Register (USARTx_GPR) (x=1/2/3/4) Chapter 15 Inter-integrated Circuit (I2C) interface 15.1 Main Features 15.2 Overview 15.3 Master Mode 15.4 Slave Mode 15.5 Error Conditions 15.5.1 Bus Error (BERR) 15.5.2 Acknowledge Failure (AF) 15.5.3 Arbitration Lost (ARLO) 15.5.4 Overrun/Underrun Error (OVR) Overrun error Underrun error 15.6 Clock Extension 15.7 Interrupts 15.8 Packet Error Checking 15.9 Register Description 15.9.1 I2C Control Register 1 (I2C1_CTLR1) 15.9.2 I2C Control Register 2 (I2C1_CTLR2) 15.9.3 I2C Address Register 1 (I2C1_OADDR1) 15.9.4 I2C Address Register 2 (I2C1_OADDR2) 15.9.5 I2C Data Register (I2C1_DATAR) 15.9.6 I2C Status Register 1 (I2C1_STAR1) 15.9.7 I2C Status Register 2 (I2C1_STAR2) 15.9.8 I2C Clock Register (I2C1_CKCFGR) Chapter 16 Serial Peripheral Interface (SPI) 16.1 Main Features 16.2 Function Description 16.2.1 Overview 16.2.2 Master Mode 16.2.3 Slave Mode 16.2.4 Simplex Mode 16.2.5 CRC 16.2.6 DMA 16.2.7 Errors 16.2.8 Interrupts 16.3 Register Description 16.3.1 SPI Control Register 1 (SPI1_CTLR1) 16.3.2 SPI Control Register 2 (SPI1_CTLR2) 16.3.3 SPI Status Register (SPI1_STATR) 16.3.4 SPI Data Register (SPI1_DATAR) 16.3.5 SPI Polynomial Register (SPI1_CRCR) 16.3.6 SPI Receive CRC Register (SPI1_RCRCR) 16.3.7 SPI Transmit CRC Register (SPI1_TCRCR) 16.3.8 SPI High-speed Control Register (SPI1_HSCR) Chapter 17 Operational Amplifiers (OPA) and Comparators (CMP) 17.1 Main Features 17.2 Function Description 17.2.1 OPA 17.2.2 Polling of Positive OPA Inputs 17.2.3 CMP 17.3 Register Description 17.3.1 OPA Configuration Register 1 (OPA_CFGR1) 17.3.2 OPA Configuration Register 2 (OPA_CFGR2) 17.3.3 OPA Control Register 1 (OPA_CTLR1) 17.3.4 OPA Control Register 2 (OPA_CTLR2) 17.3.5 OPA Unlock Key Register (OPA_KEY) 17.3.6 CMP Unlock Key Register (CMP_KEY) 17.3.7 POLL Unlock Key Register (POLL_KEY) Chapter 18 USB Full-speed Host/Device Controller (USBFS) 18.1 Introduction to USB Controller 18.2 Register Description 18.2.1 Global Register Description 18.2.1.1 USB Control Register (R8_BASE_CTRL) 18.2.1.2 USB Interrupt Enable Register (R8_INT_EN) 18.2.1.3 USB Device Address Register (R8_ DEV_ADDR) 18.2.1.4 USB Miscellaneous Status Register (R8_MIS_ST) 18.2.1.5 USB Interrupt Flag Register (R8_INT_FG) 18.2.1.6 USB Interrupt Status Register (R8_INT_ST) 18.2.1.7 USB Receive Length Register (R16_RX_LEN) 18.2.1.8 Endpoint 1 and 4 mode controller (R8_UEP4_1_MOD) 18.2.1.9 Endpoint 2 and 3 mode controller (R8_UEP2_3_MOD) 18.2.1.10 Endpoint 5, 6 and 7 mode controller (R8_UEP567_MOD) 18.2.2 USB Device Register Description 18.2.2.1 USB Device Physical Port Control Register (R8_UDEV_CTRL) 18.2.2.2 Start Address of Endpoint 0 Buffer (R32_UEP0_DMA) 18.2.2.3 Start Address of Endpoint 1 Buffer (R32_UEP1_DMA) 18.2.2.4 Start Address of Endpoint 2 Buffer (R32_UEP2_DMA) 18.2.2.5 Start Address of Endpoint 3 Buffer (R32_UEP3_DMA) 18.2.2.6 Endpoint 0 Transmit Length and Control Registers (R32_UEP0_CTRL) 18.2.2.7 Endpoint 0 transmit length register (R16_UEP0_TX_LEN) 18.2.2.8 Endpoint 0 Control Register (R16_UEP0_CTRL_H) 18.2.2.9 Endpoint 1 Transmit Length and Control Registers (R32_UEP1_CTRL) 18.2.2.10 Endpoint 1 Transmit Length Register (R16_UEP1_TX_LEN) 18.2.2.11 Endpoint 1 Control Register (R16_UEP1_CTRL_H) 18.2.2.12 Endpoint 2 Transmit Length and Control Registers (R32_UEP2_CTRL) 18.2.2.13 Endpoint 2 Transmit Length Register (R16_UEP2_TX_LEN) 18.2.2.14 Endpoint 2 Control Register (R16_UEP2_CTRL_H) 18.2.2.15 Endpoint 3 Transmit Length and Control Registers (R32_UEP3_CTRL) 18.2.2.16 Endpoint 3 Transmit Length Register (R16_UEP3_TX_LEN) 18.2.2.17 Endpoint 3 Control Register (R16_UEP3_CTRL_H) 18.2.2.18 Endpoint 4 Transmit Length and Control Registers (R32_UEP4_CTRL) 18.2.2.19 Endpoint 4 Transmit Length Register (R16_UEP4_TX_LEN) 18.2.2.20 Endpoint 4 Control Register (R16_UEP4_CTRL_H) 18.2.2.21 Start Address of Endpoint 5 Buffer (R32_UEP5_DMA) 18.2.2.22 Start Address of Endpoint 6 Buffer (R32_UEP6_DMA) 18.2.2.23 Start Address of Endpoint 7 Buffer (R32_UEP7_DMA) 18.2.2.24 Endpoint 5 Transmit Length and Control Registers (R32_UEP5_CTRL) 18.2.2.25 Endpoint 5 Transmit Length Register (R16_UEP5_TX_LEN) 18.2.2.26 Endpoint 5 Control Register (R16_UEP5_CTRL_H) 18.2.2.27 Endpoint 6 Transmit Length and Control Registers (R32_UEP6_CTRL) 18.2.2.28 Endpoint 6 Transmit Length Register (R16_UEP6_TX_LEN) 18.2.2.29 Endpoint 6 Control Register (R16_UEP6_CTRL_H) 18.2.2.30 Endpoint 7 Transmit Length and Control Registers (R32_UEP7_CTRL) 18.2.2.31 Endpoint 7 Transmit Length Register (R16_UEP7_TX_LEN) 18.2.2.32 Endpoint 7 Control Register (R16_UEP7_CTRL_H) 18.2.2.33 Endpoint X Control Register (R32_UEPX_MOD) 18.2.3 USB Host Register Description 18.2.3.1 USB Host Control Register (R8_HOST_CTRL) 18.2.3.2 USB Host Endpoint Mode Control Register (R8_HOST_EP_MOD) 18.2.3.3 USB Host Receive Buffer Start Address (R16_HOST_RX_DMA) 18.2.3.4 USB Host Transmit Buffer Start Address (R16_HOST_TX_DMA) 18.2.3.5 USB Host Auxiliary Setup Register (R8_HOST_SETUP) 18.2.3.6 USB Host Token Setup Register (R8_HOST_EP_PID) 18.2.3.7 USB Host Receive Endpoint Control Register (R8_HOST_RX_CTRL) 18.2.3.8 USB Host Transmit Length Register (R8_HOST_TX_LEN) 18.2.3.9 USB Host Transmit Endpoint Control Register (R8_HOST_TX_CTRL) Chapter 19 Electronic Signature (ESIG) 19.1 Functional Description 19.2 Register Description 19.2.1 Flash Capacity Register (ESIG_FLACAP) 19.2.2 UID Register (ESIG_UNIID1) 19.2.3 UID Register (ESIG_UNIID2) 19.2.4 UID Register (ESIG_UNIID3) Chapter 20 Flash Memory and User Option Bytes 20.1 Flash Memory Organization 20.2 Flash Memory Programming and Safety 20.2.1 Program/Erase Methods 20.2.2 Security - Protection against Illegal Access (Read, write, erase) 20.3 Register Description 20.3.1 Access Control Register (FLASH_ACTLR) 20.3.2 FPEC Key Register (FLASH_KEYR) 20.3.3 OBKEY Register (FLASH_OBKEYR) 20.3.4 Status Register (FLASH_STATR) 20.3.5 Control Register (FLASH_CTLR) 20.3.6 Address Register (FLASH_ADDR) 20.3.7 Option Byte Register (FLASH_OBR) 20.3.8 Write Protection Register (FLASH_WPR) 20.3.9 Extension Key Register (FLASH_MODEKEYR) 20.3.10 BOOT Key Register (BOOT_MODEKEYP) 20.4 Flash Operation Procedure 20.4.1 Read Operation 20.4.2 Unlock Flash Memory 20.4.3 Main Memory Standard Erase 20.4.4 Fast Programming Mode Unlock 20.4.5 Main Memory Fast Programming 20.4.6 Main Memory Fast Erase 20.5 User Option Bytes 20.5.1 User Option Bytes Unlock 20.5.2 User Option Bytes Programming 20.5.3 User Option Bytes Erase 20.5.4 Release Read Protection 20.5.5 Release Write Protection Chapter 21 USB PD Controller (USBPD) 21.1 Introduction to USB PD Controller 21.2 Register Description 21.2.1 Configuration Register (R32_USBPD_CONFIG) 21.2.2 PD Interrupt Enable Register (R16_CONFIG) 21.2.3 BMC Sample Clock Counter (R16_BMC_CLK_CNT) 21.2.4 Control Register (R32_USBPD_CONTROL) 21.2.5 PD Transceiver Control Register (R16_CONTROL) 21.2.6 PD Transceiver Enable Register (R8_CONTROL) 21.2.7 SOP Port Selection Register (R8_TX_SEL) 21.2.8 PD Transmit Length Register (R16_BMC_TX_SZ) 21.2.9 Status Register (R32_USBPD_STATUS) 21.2.10 PD Interrupt and Data Register (R16_STATUS) 21.2.11 DMA Buffer Data Register (R8_DATA_BUF) 21.2.12 PD Interrupt Flag Register (R8_STATUS) 21.2.13 Byte Counter (R16_BMC_BYTE_CNT) 21.2.14 Port Control Register (R32_USBPD_PORT) 21.2.15 CC1 Port Control Register (R16_PORT_CC1) 21.2.16 CC2 Port Control Register (R16_PORT_CC2) 21.2.17 DMA Cache Address Register (R32_USBPD_DMA) 21.2.18 PD Buffer Start Address Register (R16_DMA) Chapter 22 Programmable Protocol I/O Microcontroller (PIOC) 22.1 Main Features 22.2 Applications Chapter 23 Debug Support 23.1 Main Features 23.2 Register Description 23.2.1 Debug MCU Configuration Register (DBGMCU_CR)
VDD VPOR 20mV Hysteresis VPDR Reset lag time tRSTTEMPO Reset signal 0 1 0 2.2.2 Programmable Voltage Detector
The programmable voltage detector, PVD, is mainly used to monitor the change of the main power supply of the system and compare it with the threshold voltage set by PLS[1:0] of the power control register PWR_CTLR, and with the external interrupt register (EXTI) setting, it can generate relevant interrupts to notify the system in time for pre-power down operations such as data saving. The specific configuration is as follows. 1) Set the PLS[1:0] field of the PWR_CTLR register and select the voltage threshold to be monitored. 2) Optional interrupt handling. the PVD function is internally connected to the rising/falling edge trigger setting of line 26 of the EXTI module, turning on this interrupt (Configuring EXTI) will generate a PVD interrupt when VDD drops below the PVD threshold or rises above the PVD threshold. 3) Read the PVD0 bit of the PWR_CSR status register can obtain the current system mains power in relation to the PLS[1:0] setting threshold and perform the corresponding soft processing. Figure 2-3 Schematic diagram of PVD operation
VDD Approx. PVD 20mV Threshold value hysteresis PVD output 1 0 1
V1.9 6 Document Outline Overview Chapter 1 Memory and Bus Architecture 1.1 Bus Architecture 1.2 Memory Map 1.2.1 Memory Allocation Chapter 2 Power Control (PWR) 2.1 Overview 2.2 Power Management 2.2.1 Power-on Reset and Power-down Reset 2.2.2 Programmable Voltage Detector 2.3 Low-power Modes 2.3.1 Low-power Configuration Options 2.3.2 Sleep Mode 2.3.3 Stop Mode 2.3.4 Standby Mode 2.3.5 Auto-wakeup (AWU) 2.4 Register Description 2.4.1 Power Control Register (PWR_CTLR) 2.4.2 Power Control/Status Register (PWR_CSR) Chapter 3 Reset and Clock Control (RCC) 3.1 Main Features 3.2 Reset 3.2.1 Power Reset 3.2.2 System Reset 3.3 Clock 3.3.1 System Clock Structure 3.3.2 High-speed Clock (HSI) 3.3.3 Bus/Peripheral Clock 3.3.3.1 System Clock (SYSCLK) 3.3.3.2 HB Bus Peripheral Clock (HCLK) 3.3.3.3 Independent Watchdog Clock 3.3.3.4 Microcontroller Clock Output (MCO) 3.4 Register Description 3.4.1 Clock Control Register (RCC_CTLR) 3.4.2 Clock Configuration Register0 (RCC_CFGR0) 3.4.3 PB2 Peripheral Reset Register (RCC_APB2PRSTR) 3.4.4 PB1 Peripheral Reset Register (RCC_APB1PRSTR) 3.4.5 HB Peripheral Clock Enable Register (RCC_AHBPCENR) 3.4.6 PB2 Peripheral Clock Enable Register (RCC_APB2PCENR) 3.4.7 PB1 Peripheral Clock Enable Register (RCC_APB1PCENR) 3.4.8 Control/Status Register (RCC_RSTSCKR) 3.4.9 HB Peripheral Reset Register (RCC_AHBRSTR) Chapter 4 Auto-wakeup (AWU) 4.1 Main Features 4.2 Function Description 4.3 Register Description 4.3.1 AWU Control/Status Register (AWU_CSR) 4.3.2 AWU Wake-up Window Register (AWU_WR) 4.3.3 AWU Prescaler Register (AWU_PSC) Chapter 5 Independent Watchdog (IWDG) 5.1 Main Features 5.2 Function Description 5.2.1 Principle and Application 5.2.2 Debug Mode 5.3 Register Description 5.3.1 Control Register (IWDG_CTLR) 5.3.2 Prescaler Register (IWDG_PSCR) 5.3.3 Reload Register (IWDG_RLDR) 5.3.4 Status Register (IWDG_STATR) Chapter 6 Window Watchdog (WWDG) 6.1 Main Features 6.2 Function Description 6.2.1 Principle and Application 6.2.2 Debug Mode 6.3 Register Description 6.3.1 Control Register (WWDG_CTLR) 6.3.2 Configuration Register (WWDG_CFGR) 6.3.3 Status Register (WWDG_STATR) Chapter 7 Interrupt and Events (PFIC) 7.1 Main Features 7.1.1 PFIC 7.2 System Timer 7.3 Vector Table of Interrupts and Exceptions 7.4 External Interrupt and Event Controller (EXTI) 7.4.1 Overview 7.4.2 Wake-up Event 7.4.3 Description 7.4.4 External Event Mapping 7.5 Register Description 7.5.1 EXTI Registers 7.5.1.1 Interrupt Enable Register (EXTI_INTENR) 7.5.1.2 Event Enable Register (EXTI_EVENR) 7.5.1.3 Rising Edge Trigger Enable Register (EXTI_RTENR) 7.5.1.4 Falling Edge Trigger Enable Register (EXTI_FTENR) 7.5.1.5 Software Interrupt Event Register (EXTI_SWIEVR) 7.5.1.6 Interrupt Flag Register (EXTI_INTFR) 7.5.2 PFIC Registers 7.5.2.1 PFIC Interrupt Enable Status Register 1 (PFIC_ISR1) 7.5.2.2 PFIC Interrupt Enable Status Register 2 (PFIC_ISR2) 7.5.2.3 PFIC Interrupt Enable Status Register 3 (PFIC_ISR3) 7.5.2.4 PFIC Interrupt Enable Status Register 4 (PFIC_ISR4) 7.5.2.5 PFIC Interrupt Pending Status Register 1 (PFIC_IPR1) 7.5.2.6 PFIC Interrupt Pending Status Register 2 (PFIC_IPR2) 7.5.2.7 PFIC Interrupt Pending Status Register 3 (PFIC_IPR3) 7.5.2.8 PFIC Interrupt Pending Status Register 4 (PFIC_IPR4) 7.5.2.9 PFIC Interrupt Priority Threshold Configuration Register (PFIC_ITHRESDR) 7.5.2.10 PFIC Interrupt Configuration Register (PFIC_CFGR) 7.5.2.11 PFIC Interrupt Global Status Register (PFIC_GISR) 7.5.2.12 PFIC VTF Interrupt ID Configuration Register (PFIC_VTFIDR) 7.5.2.13 PFIC VTF Interrupt 0 Address Register (PFIC_VTFADDRR0) 7.5.2.14 PFIC VTF Interrupt 1 Address Register (PFIC_VTFADDRR1) 7.5.2.15 PFIC VTF Interrupt 2 Address Register (PFIC_VTFADDRR2) 7.5.2.16 PFIC VTF Interrupt 3 Address Register (PFIC_VTFADDRR3) 7.5.2.17 PFIC Interrupt Enable Setting Register 1 (PFIC_IENR1) 7.5.2.18 PFIC Interrupt Enable Setting Register 2 (PFIC_IENR2) 7.5.2.19 PFIC Interrupt Enable Setting Register 3 (PFIC_IENR3) 7.5.2.20 PFIC Interrupt Enable Setting Register 4 (PFIC_IENR4) 7.5.2.21 PFIC Interrupt Enable Clear Register 1 (PFIC_IRER1) 7.5.2.22 PFIC Interrupt Enable Clear Register 2 (PFIC_IRER2) 7.5.2.23 PFIC Interrupt Enable Clear Register 3 (PFIC_IRER3) 7.5.2.24 PFIC Interrupt Enable Clear Register 4 (PFIC_IRER4) 7.5.2.25 PFIC Interrupt Pending Setting Register 1 (PFIC_IPSR1) 7.5.2.26 PFIC Interrupt Pending Setting Register 2 (PFIC_IPSR2) 7.5.2.27 PFIC Interrupt Pending Setting Register 3 (PFIC_IPSR3) 7.5.2.28 PFIC Interrupt Pending Setting Register 4 (PFIC_IPSR4) 7.5.2.29 PFIC Interrupt Pending Clear Register 1 (PFIC_IPRR1) 7.5.2.30 PFIC Interrupt Pending Clear Register 2 (PFIC_IPRR2) 7.5.2.31 PFIC Interrupt Pending Clear Register 3 (PFIC_IPRR3) 7.5.2.32 PFIC Interrupt Pending Clear Register 4 (PFIC_IPRR4) 7.5.2.33 PFIC Interrupt Activation Status Register 1 (PFIC_IACTR1) 7.5.2.34 PFIC Interrupt Activation Status Register 2 (PFIC_IACTR2) 7.5.2.35 PFIC Interrupt Activation Status Register 3 (PFIC_IACTR3) 7.5.2.36 PFIC Interrupt Activation Status Register 4 (PFIC_IACTR4) 7.5.2.37 PFIC Interrupt Priority Configuration Register (PFIC_IPRIORx) (x=0-63) 7.5.2.38 PFIC System Control Register (PFIC_SCTLR) 7.5.3 Dedicated CSR Registers 7.5.3.1 Interrupt System Control Register (INTSYSCR) 7.5.3.2 Exception Entry Base Address Register (MTVEC) 7.5.4 Physical Memory Protection Unit (PMP) 7.5.4.1 PMP Configuration Register (PMPCFG0) 7.5.4.2 PMP Address 0 Register (PMPADDR0) 7.5.4.3 PMP Address 1 Register (PMPADDR1) 7.5.4.4 PMP Address 2 Register (PMPADDR2) 7.5.4.5 PMP Address 3 Register (PMPADDR3) 7.5.5 STK Register Description 7.5.5.1 System Count Control Register (STK_CTLR) 7.5.5.2 System Count Status Register (STK_SR) 7.5.5.3 System Counter Low Register (STK_CNTL) 7.5.5.4 System Counter High Register (STK_CNTH) 7.5.5.5 Counting Comparison Low Register (STK_CMPLR) 7.5.5.6 Counting Comparison High Register (STK_CMPHR) Chapter 8 GPIO and Alternate Function (GPIO/AFIO) 8.1 Main Features 8.2 Function Description 8.2.1 Overview 8.2.2 GPIO Initialization Function 8.2.3 External Interrupts 8.2.4 Alternate Functions 8.2.5 Locking Mechanism 8.2.6 Input Configuration 8.2.7 Output Configuration 8.2.8 Alternate Function Configuration 8.2.9 Analog Input Configuration 8.2.10 GPIO Settings for Peripherals 8.2.11 BC Function Configuration 8.3 Register Description 8.3.1 GPIO Register Description 8.3.1.1 Port Configuration Register Low [7:0] (GPIOx_CFGLR) (x=A/B/C) 8.3.1.2 Port Configuration Register High [15:8] (GPIOx_CFGHR) (x=A/B/C) 8.3.1.3 Port Input Data Register (GPIOx_INDR) (x=A/B/C) 8.3.1.4 Port Output Data Register (GPIOx_OUTDR) (x=A/B/C) 8.3.1.5 Port Reset/Set Register (GPIOx_BSHR) (x=A/B/C) 8.3.1.6 Port Reset Register (GPIOx_BCR) (x=A/B/C) 8.3.1.7 Port Lock Configuration Register (GPIOx_LCKR) (x=A/B/C) 8.3.1.8 GPIO Configuration Register Expansion (16-23) Bits (GPIOx_CFGXR) (x=A/B/C) 8.3.1.9 Port Set/Reset Register High (16-23) Bits (GPIOx_BSXR) (x=A/B/C) 8.3.2 AFIO Register Description 8.3.2.1 Remap Register 1 (AFIO_PCFR1) 8.3.2.2 External Interrupt Configuration Register 1 (AFIO_EXTICR1) 8.3.2.3 External Interrupt Configuration Register 2 (AFIO_EXTICR2) 8.3.2.4 Control Register (AFIO_CTLR) Chapter 9 Direct Memory Access Control (DMA) 9.1 Main Features 9.2 Function Description 9.2.1 DMA Channel Processing 9.2.2 Programmable Total Data Transfer Size/Data Bit Width/Alignment 9.2.3 DMA Request Mapping 9.3 Register Description 9.3.1 DMA Interrupt Status Register (DMA_INTFR) 9.3.2 DMA Interrupt Flag Clear Register (DMA_INTFCR) 9.3.3 DMA Channel x Configuration Register (DMA_CFGRx)(x=1/2/3/4/5/6/7/8) 9.3.4 DMA Channel x Number of Data Register (DMA_CNTRx) (x=1/2/3/4/5/6/7/8) 9.3.5 DMA Channel x Peripheral Address Register (DMA_PADDRx) (x=1/2/3/4/5/6/7/8) 9.3.6 DMA Channel x Memory Address Register (DMA_MADDRx) (x=1/2/3/4/5/6/7/8) Chapter 10 Analog-to-digital Converter (ADC) 10.1 Main Features 10.2 Functional Description 10.2.1 Module Structure 10.2.2 ADC Configuration 10.2.3 External Trigger Source 10.2.4 Conversion Mode 10.2.5 Analog Watchdog 10.3 Register Description 10.3.1 ADC Status Register (ADC_STATR) 10.3.2 ADC Control Register 1 (ADC_CTLR1) 10.3.3 ADC Control Register 2 (ADC_CTLR2) 10.3.4 ADC Sample Time Configuration Register 1 (ADC_SAMPTR1) 10.3.5 ADC Sample Time Configuration Register 2 (ADC_SAMPTR2) 10.3.6 ADC Injected Channel Data Offset Register x (ADC_IOFRx) (x=1/2/3/4) 10.3.7 ADC Watchdog High Threshold Register (ADC_WDHTR) 10.3.8 ADC Watchdog Low Threshold Register (ADC_WDLTR) 10.3.9 ADC Regular Sequence Register 1(ADC_RSQR1) 10.3.10 ADC Regular Sequence Register 2 (ADC_RSQR2) 10.3.11 ADC Regular Sequence Register 3 (ADC_RSQR3) 10.3.12 ADC Injected Sequence Register (ADC_ISQR) 10.3.13 ADC Injected Data Register (ADC_IDATARx) (x=1/2/3/4) 10.3.14 ADC Regular Data Register (ADC_RDATAR) 10.3.15 ADC Control Register 3 (ADC_CTLR3) 10.3.16 ADC Watchdog 1 Threshold Register (ADC_WDTR1) 10.3.17 ADC Watchdog 2 Threshold Register (ADC_WDTR2) 10.3.18 ADC Watchdog 3 Threshold Register (ADC_WDTR3) Chapter 11 Touch Key Detection (TKEY) 11.1 TKEY Functional Description 11.2 TKEY Operation Procedures 11.3 TKEY Register Description 11.3.1 TKEYx Charge Sample Time Register 1 (TKEYx_CHARGE1) (x=1) 11.3.2 TKEYx Charge Sample Time Register 2 (TKEYx_CHARGE2) (x=1) 11.3.3 TKEYx Charge Time Offset Register (TKEYx_CHGOFFSET) (x=1) 11.3.4 TKEYx Start and Discharge Time Register (TKEYx_ACT_DCG) (x=1) 11.3.5 TKEYx Data Register (TKEYx_DR) (x=1) Chapter 12 Advanced-control Timer (ADTM) 12.1 Main Features 12.2 Principle and Structure 12.2.1 Overview 12.2.2 Clock Input 12.2.2.1 Internal Clock Source (CK_INT) 12.2.2.2 External Clock Source Mode1 12.2.2.3 External Clock Source Mode2 12.2.2.4 Encoder Mode 12.2.3 Counters and Peripherals 12.2.4 Compare/Capture Channels and Peripherals 12.3 Function and Implementation 12.3.1 Counter Mode 12.3.2 Input Capture Mode 12.3.3 Compare Output Mode 12.3.4 Forced Output Mode 12.3.5 PWM Input Mode 12.3.6 PWM Output Mode 12.3.7 Complementary Outputs and Dead-time Insertion 12.3.8 Brake Signal 12.3.9 One-pulse Mode 12.3.10 Encoder Mode 12.3.11 Synchronization of TIMx Timers and External Triggers 12.3.12 Timer Synchronization Mode 12.3.13 Debug Mode 12.4 Register Description 12.4.1 Control Register 1 (TIMx_CTLR1) (x=1/2) 12.4.2 Control Register 2 (TIMx_CTLR2) (x=1/2) 12.4.3 Slave Mode Control Register (TIMx_SMCFGR) (x=1/2) 12.4.4 DMA/Interrupt Enable Register (TIMx_DMAINTENR) (x=1/2) 12.4.5 Interrupt Status Register (TIMx_INTFR) (x=1/2) 12.4.6 Event Generation Register (TIMx_SWEVGR) (x=1/2) 12.4.7 Compare/Capture Control Register 1 (TIMx_CHCTLR1) (x=1/2) 12.4.8 Compare/Capture Control Register 2 (TIMx_CHCTLR2) (x=1/2) 12.4.9 Compare/Capture Enable Register 2 (TIMx_CCER) (x=1/2) 12.4.10 Counter for Advanced-control Timer (TIMx_CNT) (x=1/2) 12.4.11 Counting Clock Prescaler (TIMx_PSC) (x=1/2) 12.4.12 Auto-reload Value Register (TIMx_ATRLR) (x=1/2) 12.4.13 Repeat Count Value Register (TIMx_RPTCR) (x=1/2) 12.4.14 Compare/Capture Register 1 (TIMx_CH1CVR) (x=1/2) 12.4.15 Compare/Capture Register 2 (TIMx_CH2CVR) (x=1/2) 12.4.16 Compare/Capture Register 3 (TIMx_CH3CVR) (x=1/2) 12.4.17 Compare/Capture Register 4 (TIMx_CH4CVR) (x=1/2) 12.4.18 Brake and Dead-time Register (TIMx_BDTR) (x=1/2) 12.4.19 DMA Control Register (TIMx_DMACFGR) (x=1/2) 12.4.20 DMA Address Register for Continuous Mode (TIMx_DMAADR) (x=1/2) 12.4.21 SPEC Register (TIMx_SPEC) (x=1/2) Chapter 13 General-Purpose Timer (GPTM) 13.1 Main Features 13.2 Principle and Structure 13.2.1 Overview 13.2.2 Differences between General-Purpose Timer and Advanced-Control Timer 13.2.3 Clock Input 13.2.3.1 Internal Clock Source (CK_INT) 13.2.3.2 External Clock Source Mode 1 13.2.4 Counters and Peripherals 13.2.5 Compare/capture Channels 13.3 Function and Implementation 13.3.1 Counter Mode 13.3.2 Input Capture Mode 13.3.3 Compare Output Mode 13.3.4 Forced Output Mode 13.3.5 PWM Input Mode 13.3.6 PWM Output Mode 13.3.7 Single Pulse Mode 13.3.8 Synchronization of TIMx Timers and External Triggers 13.3.10 Debug mode 13.4 Register Description 13.4.1 Control Register 1 (TIM3_CTLR1) 13.4.2 Slave Mode Control Register (TIM3_SMCFGR) 13.4.3 DMA/Interrupt Enable Register (TIM3_DMAINTENR) 13.4.4 Interrupt Status Register (TIM3_INTFR) 13.4.5 Event Generation Register (TIM3_SWEVGR) 13.4.6 Compare/Capture Control Register 1 (TIM3_CHCTLR1) 13.4.7 Compare/Capture Enable Register (TIM3_CCER) 13.4.8 Counter for General-purpose Timer (TIM3_CNT) 13.4.9 Counting Clock Prescaler (TIM3_PSC) 13.4.10 Auto-reload Value Register (TIM3_ATRLR) 13.4.11 Compare/Capture Register 1 (TIM3_CH1CVR) 13.4.12 Compare/Capture Register 2 (TIM3_CH2CVR) 13.4.13 SPEC Register (TIM3_SPEC) Chapter 14 Universal Synchronous Asynchronous Receiver Transmitter (USART) 14.1 Main Features 14.2 Overview 14.3 Baud Rate Generator 14.4 Synchronous Mode 14.5 1-Wire Half-Duplex Mode 14.6 Smart Card 14.7 IrDA 14.8 DMA 14.9 Interrupts 14.10 Register Description 14.10.1 USART Status Register (USARTx_STATR) (x=1/2/3/4) 14.10.2 USART Data Register (USARTx_DATAR) (x=1/2/3/4) 14.10.3 USART Baud Rate Register (USARTx_BRR) (x=1/2/3/4) 14.10.4 USART Control Register 1 (USARTx_CTLR1) (x=1/2/3/4) 14.10.5 USART Control Register 2 (USARTx_CTLR2) (x=1/2/3/4) 14.10.6 USART Control Register 3 (USARTx_CTLR3) (x=1/2/3/4) 14.10.7 USART Guard Time and Prescaler Register (USARTx_GPR) (x=1/2/3/4) Chapter 15 Inter-integrated Circuit (I2C) interface 15.1 Main Features 15.2 Overview 15.3 Master Mode 15.4 Slave Mode 15.5 Error Conditions 15.5.1 Bus Error (BERR) 15.5.2 Acknowledge Failure (AF) 15.5.3 Arbitration Lost (ARLO) 15.5.4 Overrun/Underrun Error (OVR) Overrun error Underrun error 15.6 Clock Extension 15.7 Interrupts 15.8 Packet Error Checking 15.9 Register Description 15.9.1 I2C Control Register 1 (I2C1_CTLR1) 15.9.2 I2C Control Register 2 (I2C1_CTLR2) 15.9.3 I2C Address Register 1 (I2C1_OADDR1) 15.9.4 I2C Address Register 2 (I2C1_OADDR2) 15.9.5 I2C Data Register (I2C1_DATAR) 15.9.6 I2C Status Register 1 (I2C1_STAR1) 15.9.7 I2C Status Register 2 (I2C1_STAR2) 15.9.8 I2C Clock Register (I2C1_CKCFGR) Chapter 16 Serial Peripheral Interface (SPI) 16.1 Main Features 16.2 Function Description 16.2.1 Overview 16.2.2 Master Mode 16.2.3 Slave Mode 16.2.4 Simplex Mode 16.2.5 CRC 16.2.6 DMA 16.2.7 Errors 16.2.8 Interrupts 16.3 Register Description 16.3.1 SPI Control Register 1 (SPI1_CTLR1) 16.3.2 SPI Control Register 2 (SPI1_CTLR2) 16.3.3 SPI Status Register (SPI1_STATR) 16.3.4 SPI Data Register (SPI1_DATAR) 16.3.5 SPI Polynomial Register (SPI1_CRCR) 16.3.6 SPI Receive CRC Register (SPI1_RCRCR) 16.3.7 SPI Transmit CRC Register (SPI1_TCRCR) 16.3.8 SPI High-speed Control Register (SPI1_HSCR) Chapter 17 Operational Amplifiers (OPA) and Comparators (CMP) 17.1 Main Features 17.2 Function Description 17.2.1 OPA 17.2.2 Polling of Positive OPA Inputs 17.2.3 CMP 17.3 Register Description 17.3.1 OPA Configuration Register 1 (OPA_CFGR1) 17.3.2 OPA Configuration Register 2 (OPA_CFGR2) 17.3.3 OPA Control Register 1 (OPA_CTLR1) 17.3.4 OPA Control Register 2 (OPA_CTLR2) 17.3.5 OPA Unlock Key Register (OPA_KEY) 17.3.6 CMP Unlock Key Register (CMP_KEY) 17.3.7 POLL Unlock Key Register (POLL_KEY) Chapter 18 USB Full-speed Host/Device Controller (USBFS) 18.1 Introduction to USB Controller 18.2 Register Description 18.2.1 Global Register Description 18.2.1.1 USB Control Register (R8_BASE_CTRL) 18.2.1.2 USB Interrupt Enable Register (R8_INT_EN) 18.2.1.3 USB Device Address Register (R8_ DEV_ADDR) 18.2.1.4 USB Miscellaneous Status Register (R8_MIS_ST) 18.2.1.5 USB Interrupt Flag Register (R8_INT_FG) 18.2.1.6 USB Interrupt Status Register (R8_INT_ST) 18.2.1.7 USB Receive Length Register (R16_RX_LEN) 18.2.1.8 Endpoint 1 and 4 mode controller (R8_UEP4_1_MOD) 18.2.1.9 Endpoint 2 and 3 mode controller (R8_UEP2_3_MOD) 18.2.1.10 Endpoint 5, 6 and 7 mode controller (R8_UEP567_MOD) 18.2.2 USB Device Register Description 18.2.2.1 USB Device Physical Port Control Register (R8_UDEV_CTRL) 18.2.2.2 Start Address of Endpoint 0 Buffer (R32_UEP0_DMA) 18.2.2.3 Start Address of Endpoint 1 Buffer (R32_UEP1_DMA) 18.2.2.4 Start Address of Endpoint 2 Buffer (R32_UEP2_DMA) 18.2.2.5 Start Address of Endpoint 3 Buffer (R32_UEP3_DMA) 18.2.2.6 Endpoint 0 Transmit Length and Control Registers (R32_UEP0_CTRL) 18.2.2.7 Endpoint 0 transmit length register (R16_UEP0_TX_LEN) 18.2.2.8 Endpoint 0 Control Register (R16_UEP0_CTRL_H) 18.2.2.9 Endpoint 1 Transmit Length and Control Registers (R32_UEP1_CTRL) 18.2.2.10 Endpoint 1 Transmit Length Register (R16_UEP1_TX_LEN) 18.2.2.11 Endpoint 1 Control Register (R16_UEP1_CTRL_H) 18.2.2.12 Endpoint 2 Transmit Length and Control Registers (R32_UEP2_CTRL) 18.2.2.13 Endpoint 2 Transmit Length Register (R16_UEP2_TX_LEN) 18.2.2.14 Endpoint 2 Control Register (R16_UEP2_CTRL_H) 18.2.2.15 Endpoint 3 Transmit Length and Control Registers (R32_UEP3_CTRL) 18.2.2.16 Endpoint 3 Transmit Length Register (R16_UEP3_TX_LEN) 18.2.2.17 Endpoint 3 Control Register (R16_UEP3_CTRL_H) 18.2.2.18 Endpoint 4 Transmit Length and Control Registers (R32_UEP4_CTRL) 18.2.2.19 Endpoint 4 Transmit Length Register (R16_UEP4_TX_LEN) 18.2.2.20 Endpoint 4 Control Register (R16_UEP4_CTRL_H) 18.2.2.21 Start Address of Endpoint 5 Buffer (R32_UEP5_DMA) 18.2.2.22 Start Address of Endpoint 6 Buffer (R32_UEP6_DMA) 18.2.2.23 Start Address of Endpoint 7 Buffer (R32_UEP7_DMA) 18.2.2.24 Endpoint 5 Transmit Length and Control Registers (R32_UEP5_CTRL) 18.2.2.25 Endpoint 5 Transmit Length Register (R16_UEP5_TX_LEN) 18.2.2.26 Endpoint 5 Control Register (R16_UEP5_CTRL_H) 18.2.2.27 Endpoint 6 Transmit Length and Control Registers (R32_UEP6_CTRL) 18.2.2.28 Endpoint 6 Transmit Length Register (R16_UEP6_TX_LEN) 18.2.2.29 Endpoint 6 Control Register (R16_UEP6_CTRL_H) 18.2.2.30 Endpoint 7 Transmit Length and Control Registers (R32_UEP7_CTRL) 18.2.2.31 Endpoint 7 Transmit Length Register (R16_UEP7_TX_LEN) 18.2.2.32 Endpoint 7 Control Register (R16_UEP7_CTRL_H) 18.2.2.33 Endpoint X Control Register (R32_UEPX_MOD) 18.2.3 USB Host Register Description 18.2.3.1 USB Host Control Register (R8_HOST_CTRL) 18.2.3.2 USB Host Endpoint Mode Control Register (R8_HOST_EP_MOD) 18.2.3.3 USB Host Receive Buffer Start Address (R16_HOST_RX_DMA) 18.2.3.4 USB Host Transmit Buffer Start Address (R16_HOST_TX_DMA) 18.2.3.5 USB Host Auxiliary Setup Register (R8_HOST_SETUP) 18.2.3.6 USB Host Token Setup Register (R8_HOST_EP_PID) 18.2.3.7 USB Host Receive Endpoint Control Register (R8_HOST_RX_CTRL) 18.2.3.8 USB Host Transmit Length Register (R8_HOST_TX_LEN) 18.2.3.9 USB Host Transmit Endpoint Control Register (R8_HOST_TX_CTRL) Chapter 19 Electronic Signature (ESIG) 19.1 Functional Description 19.2 Register Description 19.2.1 Flash Capacity Register (ESIG_FLACAP) 19.2.2 UID Register (ESIG_UNIID1) 19.2.3 UID Register (ESIG_UNIID2) 19.2.4 UID Register (ESIG_UNIID3) Chapter 20 Flash Memory and User Option Bytes 20.1 Flash Memory Organization 20.2 Flash Memory Programming and Safety 20.2.1 Program/Erase Methods 20.2.2 Security - Protection against Illegal Access (Read, write, erase) 20.3 Register Description 20.3.1 Access Control Register (FLASH_ACTLR) 20.3.2 FPEC Key Register (FLASH_KEYR) 20.3.3 OBKEY Register (FLASH_OBKEYR) 20.3.4 Status Register (FLASH_STATR) 20.3.5 Control Register (FLASH_CTLR) 20.3.6 Address Register (FLASH_ADDR) 20.3.7 Option Byte Register (FLASH_OBR) 20.3.8 Write Protection Register (FLASH_WPR) 20.3.9 Extension Key Register (FLASH_MODEKEYR) 20.3.10 BOOT Key Register (BOOT_MODEKEYP) 20.4 Flash Operation Procedure 20.4.1 Read Operation 20.4.2 Unlock Flash Memory 20.4.3 Main Memory Standard Erase 20.4.4 Fast Programming Mode Unlock 20.4.5 Main Memory Fast Programming 20.4.6 Main Memory Fast Erase 20.5 User Option Bytes 20.5.1 User Option Bytes Unlock 20.5.2 User Option Bytes Programming 20.5.3 User Option Bytes Erase 20.5.4 Release Read Protection 20.5.5 Release Write Protection Chapter 21 USB PD Controller (USBPD) 21.1 Introduction to USB PD Controller 21.2 Register Description 21.2.1 Configuration Register (R32_USBPD_CONFIG) 21.2.2 PD Interrupt Enable Register (R16_CONFIG) 21.2.3 BMC Sample Clock Counter (R16_BMC_CLK_CNT) 21.2.4 Control Register (R32_USBPD_CONTROL) 21.2.5 PD Transceiver Control Register (R16_CONTROL) 21.2.6 PD Transceiver Enable Register (R8_CONTROL) 21.2.7 SOP Port Selection Register (R8_TX_SEL) 21.2.8 PD Transmit Length Register (R16_BMC_TX_SZ) 21.2.9 Status Register (R32_USBPD_STATUS) 21.2.10 PD Interrupt and Data Register (R16_STATUS) 21.2.11 DMA Buffer Data Register (R8_DATA_BUF) 21.2.12 PD Interrupt Flag Register (R8_STATUS) 21.2.13 Byte Counter (R16_BMC_BYTE_CNT) 21.2.14 Port Control Register (R32_USBPD_PORT) 21.2.15 CC1 Port Control Register (R16_PORT_CC1) 21.2.16 CC2 Port Control Register (R16_PORT_CC2) 21.2.17 DMA Cache Address Register (R32_USBPD_DMA) 21.2.18 PD Buffer Start Address Register (R16_DMA) Chapter 22 Programmable Protocol I/O Microcontroller (PIOC) 22.1 Main Features 22.2 Applications Chapter 23 Debug Support 23.1 Main Features 23.2 Register Description 23.2.1 Debug MCU Configuration Register (DBGMCU_CR)