Datasheet DCL320C00 (Toshiba) - 7
| Manufacturer | Toshiba |
| Description | Low power, 25Mbps mid speed, 2 channel Digital Isolator in SOIC8-N package |
| Pages / Page | 21 / 7 — 9.2. Electrical Characteristics – 3.3 V Supply. 10Mbps. 25Mbps |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
9.2. Electrical Characteristics – 3.3 V Supply. 10Mbps. 25Mbps
Model Line for this Datasheet
Text Version of Document
DCL32xx00
9.2. Electrical Characteristics – 3.3 V Supply
All typical specifications are at Ta = 25 °C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and -40 °C ≤ Ta ≤ 125 °C, unless otherwise noted. PARAMETER TEST CONDITIONS Fig. SYMBOL MIN TYP. MAX UNIT DC SPECIFICATIONS Output Voltage V (Note1) (Note1) IX = H , IOH = -20 μA VDDO -0.1 VDDO - Fig.12.1 V V Logic High OH V (Note1) (Note1) IX = H , IOH = -4 mA VDDO -0.4 VDDO -0.2 - Output Voltage VIX = L , IOL = 20 μA - 0.0 0.1 Fig.12.1 V V Logic Low OL VIX = L , IOL = 4 mA - 0.2 0.4 Output impedance - Fig.12.1 ZO - 50 - Ω High-level input voltage - Fig.12.2 V (Note1) IH 0.7*VDDI - - V Low-level input voltage - Fig.12.2 V (Note1) IL - - 0.3*VDDI V Input Voltage Hysteresis - Fig.12.2 VHYS - 0.25 - V Input Current V (Note1) I = VDDI or 0 V - II - - ±1 μA SWITCHING SPECIFICATIONS Data Rate - - tbps DC - 25 Mbps Pulse Width - - PW 40 - - ns 50 kHz, Duty = 50 %, Propagation Delay Fig.12.3 t t PHL , tPLH - 38 52 ns r = tf= 2 ns, CL = 15 pF
DC
～
10Mbps
Pulse Width Distortion |tPHL – tPLH| Fig.12.3 PWD - 0.7 8.0 ns Propagation Delay Skew(Note2) - - t (Between any two units) PSK - - 19 ns Same Direction Fig.12.3 tskCD - - 5.0 Channel Matching ns Opposing Direction Fig.12.3 tskOD - - 9.0
DC
～
25Mbps
Pulse Width Distortion |tPHL – tPLH| Fig.12.3 PWD - 0.7 13 ns Propagation Delay Skew(Note2) - - t (Between any two units) PSK - - 24 ns Same Direction Fig.12.3 tskCD - - 10 Channel Matching ns Opposing Direction Fig.12.3 tskOD - - 14 Output Rise Time 10 % - 90 % Fig.12.3 tr - 2.0 - ns Output Fall Time 90 % - 10 % Fig.12.3 tf - 2.0 - ns Default output delay time from input V power loss DDI < 2.25 V → 0 V - tDO - - 30 μs Time from PU(Note3) to valid output - - t data PU - - 30 μs Common mode transient immunity VI = VDDI or 0 V , Fig. 12.4 |CMTI| 30 - - kV/μs (Note4) VCM = 400 V, Ta = 25°C Note1: VDDI = Input-side VDDX , VDDO = Output-side VDDX Note2: Propagation delay difference (between parts) is applied under the same operating conditions (power supply voltage. input current, temperature conditions, etc.). Note3: PU = Powered up (VDD ≥ 2.25 V) , After VDD is set powered up, normal operation become valid 30μs later. Note4: This parameter is warranted by design. © 2 0 2 6 7 2026-09-08 Toshiba Electronic Devices & Storage Corporation Rev.1.8
9.2. Electrical Characteristics – 3.3 V Supply
All typical specifications are at Ta = 25 °C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended operating range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and -40 °C ≤ Ta ≤ 125 °C, unless otherwise noted. PARAMETER TEST CONDITIONS Fig. SYMBOL MIN TYP. MAX UNIT DC SPECIFICATIONS Output Voltage V (Note1) (Note1) IX = H , IOH = -20 μA VDDO -0.1 VDDO - Fig.12.1 V V Logic High OH V (Note1) (Note1) IX = H , IOH = -4 mA VDDO -0.4 VDDO -0.2 - Output Voltage VIX = L , IOL = 20 μA - 0.0 0.1 Fig.12.1 V V Logic Low OL VIX = L , IOL = 4 mA - 0.2 0.4 Output impedance - Fig.12.1 ZO - 50 - Ω High-level input voltage - Fig.12.2 V (Note1) IH 0.7*VDDI - - V Low-level input voltage - Fig.12.2 V (Note1) IL - - 0.3*VDDI V Input Voltage Hysteresis - Fig.12.2 VHYS - 0.25 - V Input Current V (Note1) I = VDDI or 0 V - II - - ±1 μA SWITCHING SPECIFICATIONS Data Rate - - tbps DC - 25 Mbps Pulse Width - - PW 40 - - ns 50 kHz, Duty = 50 %, Propagation Delay Fig.12.3 t t PHL , tPLH - 38 52 ns r = tf= 2 ns, CL = 15 pF
DC
～
10Mbps
Pulse Width Distortion |tPHL – tPLH| Fig.12.3 PWD - 0.7 8.0 ns Propagation Delay Skew(Note2) - - t (Between any two units) PSK - - 19 ns Same Direction Fig.12.3 tskCD - - 5.0 Channel Matching ns Opposing Direction Fig.12.3 tskOD - - 9.0
DC
～
25Mbps
Pulse Width Distortion |tPHL – tPLH| Fig.12.3 PWD - 0.7 13 ns Propagation Delay Skew(Note2) - - t (Between any two units) PSK - - 24 ns Same Direction Fig.12.3 tskCD - - 10 Channel Matching ns Opposing Direction Fig.12.3 tskOD - - 14 Output Rise Time 10 % - 90 % Fig.12.3 tr - 2.0 - ns Output Fall Time 90 % - 10 % Fig.12.3 tf - 2.0 - ns Default output delay time from input V power loss DDI < 2.25 V → 0 V - tDO - - 30 μs Time from PU(Note3) to valid output - - t data PU - - 30 μs Common mode transient immunity VI = VDDI or 0 V , Fig. 12.4 |CMTI| 30 - - kV/μs (Note4) VCM = 400 V, Ta = 25°C Note1: VDDI = Input-side VDDX , VDDO = Output-side VDDX Note2: Propagation delay difference (between parts) is applied under the same operating conditions (power supply voltage. input current, temperature conditions, etc.). Note3: PU = Powered up (VDD ≥ 2.25 V) , After VDD is set powered up, normal operation become valid 30μs later. Note4: This parameter is warranted by design. © 2 0 2 6 7 2026-09-08 Toshiba Electronic Devices & Storage Corporation Rev.1.8