Datasheet OP270 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Dual Very Low Noise Precision Operational Amplifier |
| Pages / Page | 20 / 4 — OP270. Data Sheet. ELECTRICAL SPECIFICATIONS. Table 2. OP270E. OP270F. … |
| Revision | F |
| File Format / Size | PDF / 329 Kb |
| Document Language | English |
OP270. Data Sheet. ELECTRICAL SPECIFICATIONS. Table 2. OP270E. OP270F. OP270G. Parameter Symbol. Test. Conditions
Model Line for this Datasheet
Text Version of Document
OP270 Data Sheet ELECTRICAL SPECIFICATIONS
VS = ±15 V, −40°C ≤ TA ≤ 85°C, unless otherwise noted.
Table 2. OP270E OP270F OP270G Parameter Symbol Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS 25 150 45 275 100 400 μV Average Input Offset TCVOS 0.2 1 0.4 2 0.7 3 μV/°C Voltage Drift Input Offset Current IOS VCM = 0 V 1.5 30 5 40 15 50 nA Input Bias Voltage IB VCM = 0 V 6 60 15 70 19 80 nA Large-Signal Voltage Gain AVO VO = ±10 V, 1000 1800 600 1400 400 1250 V/mV RL = 10 kΩ AVO VO = ±10 V, 500 900 300 700 225 670 V/mV RL = 2 kΩ Input Voltage Range1 IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V Output Voltage Swing VO RL ≥ 2 kΩ ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 V Common-Mode Rejection CMR VCM = ±11 V 100 120 94 115 90 100 dB Power Supply Rejection PSRR VS = ±4.5 V to ±18 V 0.7 5.6 1.8 10 2.0 1.5 μV/V Ratio Supply Current ISY No load 4.4 7.2 4.4 7.2 4.4 7.2 mA (All Amplifiers) 1 Guaranteed by CMR test. Rev. F | Page 4 of 20 Document Outline Features Functional Block Diagrams General Description Table of Contents Revision History Specifications Electrical Specifications Absolute Maximum Ratings ESD Caution Typical Performance Characteristics Test Circuits Applications Information Voltage and Current Noise Total Noise and Source Resistance Noise Measurements Peak-to-Peak Voltage Noise Noise Measurement—Noise Voltage Density Noise Measurement—Current Noise Density Capacitive Load Driving and Power Supply Considerations Unity-Gain Buffer Applications Low Phase Error Amplifier Five-Band, Low Noise, Stereo Graphic Equalizer Digital Panning Control Dual Programmable Gain Amplifier Outline Dimensions Ordering Guide
VS = ±15 V, −40°C ≤ TA ≤ 85°C, unless otherwise noted.
Table 2. OP270E OP270F OP270G Parameter Symbol Test Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS 25 150 45 275 100 400 μV Average Input Offset TCVOS 0.2 1 0.4 2 0.7 3 μV/°C Voltage Drift Input Offset Current IOS VCM = 0 V 1.5 30 5 40 15 50 nA Input Bias Voltage IB VCM = 0 V 6 60 15 70 19 80 nA Large-Signal Voltage Gain AVO VO = ±10 V, 1000 1800 600 1400 400 1250 V/mV RL = 10 kΩ AVO VO = ±10 V, 500 900 300 700 225 670 V/mV RL = 2 kΩ Input Voltage Range1 IVR ±12 ±12.5 ±12 ±12.5 ±12 ±12.5 V Output Voltage Swing VO RL ≥ 2 kΩ ±12 ±13.5 ±12 ±13.5 ±12 ±13.5 V Common-Mode Rejection CMR VCM = ±11 V 100 120 94 115 90 100 dB Power Supply Rejection PSRR VS = ±4.5 V to ±18 V 0.7 5.6 1.8 10 2.0 1.5 μV/V Ratio Supply Current ISY No load 4.4 7.2 4.4 7.2 4.4 7.2 mA (All Amplifiers) 1 Guaranteed by CMR test. Rev. F | Page 4 of 20 Document Outline Features Functional Block Diagrams General Description Table of Contents Revision History Specifications Electrical Specifications Absolute Maximum Ratings ESD Caution Typical Performance Characteristics Test Circuits Applications Information Voltage and Current Noise Total Noise and Source Resistance Noise Measurements Peak-to-Peak Voltage Noise Noise Measurement—Noise Voltage Density Noise Measurement—Current Noise Density Capacitive Load Driving and Power Supply Considerations Unity-Gain Buffer Applications Low Phase Error Amplifier Five-Band, Low Noise, Stereo Graphic Equalizer Digital Panning Control Dual Programmable Gain Amplifier Outline Dimensions Ordering Guide
