Industry-First Advancement Can Improve Performance, Conserve Power in Future Single- and Multi-Core Processors
AMD and IBM announced that they have developed a new and unique strained silicon transistor technology aimed at improving processor performance and power efficiency. The breakthrough process results in up to a 24 percent transistor speed increase, at the same power levels, compared to similar transistors produced without the technology.Faster, more power-efficient transistors are the building blocks of higher performance, lower power processors. As transistors get smaller, they operate faster, but also risk operating at higher power and heat levels due to electrical leakage or inefficient switching. AMD and IBM's jointly developed strained silicon helps overcome these challenges. In addition, this process makes AMD and IBM the first companies to introduce strained silicon that works with silicon-on-insulator (SOI) technology, resulting in an additive performance and power savings benefit.
AMD intends to gradually integrate the new strained silicon technology into all of its 90nm processor platforms, including its future multi-core AMD64 processors. AMD plans to ship the first 90nm AMD64 processors using the technology in the first half of 2005.
IBM plans to introduce the technology on multiple 90nm processor platforms, including its Power Architecture-based chips, with the first products slated to begin shipping in the first half of 2005.
The new strained silicon process, called "Dual Stress Liner," enhances the performance of both types of semiconductor transistors, called n-channel and p-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other. The dual stress liner technique works without the introduction of challenging, costly new production techniques, allowing for its rapid integration into volume manufacturing using standard tools and materials.
AMD and IBM researchers are the first in the industry to simultaneously enhance the performance of both types of transistors in a semiconductor using conventional materials.
The Dual Stress Liner with SOI technology was developed by engineers from IBM, AMD, Sony and Toshiba at IBM's Semiconductor Research and Development Center (SRDC) in East Fishkill, NY, as well as engineers from AMD at its Fab 30 facility in Dresden, Germany.
IBM and AMD have been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003.
