I2C interface has galvanic isolation, wired-OR capability, improved noise margin

Michele Costantino

EDN

This Design Idea describes a simple and effective way to provide optoisolation for devices connected on the I²C bus (Figure 1). It improves on an earlier version (Reference 1). SDA and SCL are on the bus master’s side of the I²C bus; SDA₁ and SCL₁ are on the slave device’s side. It is fairly easy to optoisolate the clock line because it is unidirectional, from the master to the slave device. A P-channel MOSFET, Q₃, provides the current for the LED of the fast optocoupler, IC₂, buffering the clock line.

Figure 1.	This circuit provides an isolated, bidirectional, wired-OR connection of slave devices to the I2C-bus master.

The data line, however, is bidirectional. This section of the circuit is symmetrical. Resistors R₆ and R₇ are the I²C pullup resistors on the slave device’s side of the bus, and R₃ and R₁ are dummy pullups in parallel with the main I²C pullup resistors on the SDA/SCL side. If both SDA and SDA₁ lines are high – that is, no I²C devices are pulling them down – Q₁ is off, no current flows into the LED of optocoupler IC₂, IC₂’s Pin 7 is high, Q₂ is off, and the LED of optocoupler IC₁ is also off.

If a device drives the SDA line low, Q₁ and the LED of IC₂ turn off, driving IC₂’s Pin 7 low; diode D₂ then starts to conduct. The result is a low level on the SDA₁ line – the low output voltage of IC₂ plus the threshold voltage of Schottky barrier diode D₂. In this situation, it is important to notice that the LED of IC₁ does not turn on because the voltage applied across it is below its threshold. This situation means that the circuit does not latch, and it can recover from this state once you release the SDA line.

Q₃ and the PNP BJT (bipolar-junction transistor), Q₁, effectively buffer the two SDA/SCL lines so that no extra current flows into the open-collector and -drain stages of the I²C devices that connect to the bus when they hold the lines down. This configuration allows the optoisolated interface to repeatedly pull low, providing wired-OR capability. Using Schottky barrier diodes for D₁ and D₂ rather than common diodes reduces the low-level voltage on the bus, improving the noise margin. Finally, because of the low propagation-delay times of the HCPL06XX devices that this design uses, this interface has no bus-glitch problems and works well at speeds of 400 kHz or higher (Reference 2).

References

Materials on the topic