Datasheet Texas Instruments ADS5542

Manufacturer	Texas Instruments
Series	ADS5542

Datasheets

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Status

Packaging

Parametrics

Parameters / Models	ADS5542IPAP	ADS5542IPAPR	ADS5542IPAPRG4
# Input Channels	1	1	1
Analog Input BW, MHz	750
Analog Input BW(MHz)		750	750
Approx. Price (US$)		39.81 | 1ku	39.81 | 1ku
Architecture	Pipeline	Pipeline	Pipeline
DNL(Max), +/-LSB	0.5
DNL(Max)(+/-LSB)		0.5	0.5
DNL(Typ), +/-LSB	0.5
ENOB, Bits	11.7
ENOB(Bits)		11.7	11.7
INL(Max), +/-LSB	2
INL(Max)(+/-LSB)		2	2
INL(Typ), +/-LSB	2
Input Buffer	No	No	No
Input Range	2.3	2.3V (p-p)	2.3V (p-p)
Interface	Parallel CMOS	Parallel CMOS Serial SPI Interface	Parallel CMOS Serial SPI Interface
Operating Temperature Range, C	-40 to 85
Operating Temperature Range(C)		-40 to 85	-40 to 85
Package Group	HTQFP	HTQFP	HTQFP
Package Size: mm2:W x L, PKG	64HTQFP: 144 mm2: 12 x 12(HTQFP)
Package Size: mm2:W x L (PKG)		64HTQFP: 144 mm2: 12 x 12(HTQFP)	64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW	674
Power Consumption(Typ)(mW)		674	674
Rating	Catalog	Catalog	Catalog
Reference Mode	Int	Int	Int
Resolution, Bits	14
Resolution(Bits)		14	14
SFDR, dB	87
SFDR(dB)		87	87
SINAD, dB	73.2
SINAD(dB)		73.2	73.2
SNR, dB	73.5
SNR(dB)		73.5	73.5
Sample Rate(Max), MSPS	80
Sample Rate(Max)(MSPS)		80	80

Eco Plan

Application Notes

• Download
  Clocking High-Speed Data Converters
  PDF, 310 Kb, File published: Jan 18, 2005
• Download
  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
• Download
  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
• Download
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, File published: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Download
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, File published: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Download
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Download
  Interleaving Analog-to-Digital Converters
  PDF, 64 Kb, File published: Oct 2, 2000
  It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
• Download
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
• Download
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
• Download
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revision: A, File published: May 18, 2015
• Download
  What Designers Should Know About Data Converter Drift
  PDF, 95 Kb, File published: Oct 2, 2000
  Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.

Model Line

Manufacturer's Classification

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)