Datasheet Texas Instruments SN74ALVC244

Manufacturer	Texas Instruments
Series	SN74ALVC244

Octal Buffer/Driver With 3-State OUtputs

Datasheets

Download

PDF, 1.3 Mb, Revision: G, File published: Aug 31, 2004

Extract from the document

Prices

Status

	SN74ALVC244DGVR	SN74ALVC244DGVRG4	SN74ALVC244DW	SN74ALVC244DWG4	SN74ALVC244DWR	SN74ALVC244DWRE4	SN74ALVC244DWRG4	SN74ALVC244NSR	SN74ALVC244NSRE4	SN74ALVC244PW	SN74ALVC244PWE4	SN74ALVC244PWR	SN74ALVC244PWRE4	SN74ALVC244RGYR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	No	No	No	No	Yes	No	No

Packaging

	SN74ALVC244DGVR	SN74ALVC244DGVRG4	SN74ALVC244DW	SN74ALVC244DWG4	SN74ALVC244DWR	SN74ALVC244DWRE4	SN74ALVC244DWRG4	SN74ALVC244NSR	SN74ALVC244NSRE4	SN74ALVC244PW	SN74ALVC244PWE4	SN74ALVC244PWR	SN74ALVC244PWRE4	SN74ALVC244RGYR
N	1	2	3	4	5	6	7	8	9	10	11	12	13	14
Pin	20	20	20	20	20	20	20	20	20	20	20	20	20	20
Package Type	DGV	DGV	DW	DW	DW	DW	DW	NS	NS	PW	PW	PW	PW	RGY
Industry STD Term	TVSOP	TVSOP	SOIC	SOIC	SOIC	SOIC	SOIC	SOP	SOP	TSSOP	TSSOP	TSSOP	TSSOP	VQFN
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PQFP-N
Package QTY	2000	2000	25	25	2000	2000	2000	2000	2000	70	70	2000	2000	3000
Carrier	LARGE T&R	LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R
Device Marking	VA244	VA244	ALVC244	ALVC244	ALVC244	ALVC244	ALVC244	ALVC244	ALVC244	VA244	VA244	VA244	VA244	VA244
Width (mm)	4.4	4.4	7.5	7.5	7.5	7.5	7.5	5.3	5.3	4.4	4.4	4.4	4.4	3.5
Length (mm)	5	5	12.8	12.8	12.8	12.8	12.8	12.6	12.6	6.5	6.5	6.5	6.5	4.5
Thickness (mm)	1.05	1.05	2.35	2.35	2.35	2.35	2.35	1.95	1.95	1	1	1	1	.9
Pitch (mm)	.4	.4	1.27	1.27	1.27	1.27	1.27	1.27	1.27	.65	.65	.65	.65	.5
Max Height (mm)	1.2	1.2	2.65	2.65	2.65	2.65	2.65	2	2	1.2	1.2	1.2	1.2	1
Mechanical Data	Download	Download	Download	Download	Download	Download	Download	Download	Download	Download	Download	Download	Download	Download

Parametrics

Parameters / Models	SN74ALVC244DGVR	SN74ALVC244DGVRG4	SN74ALVC244DW	SN74ALVC244DWG4	SN74ALVC244DWR	SN74ALVC244DWRE4	SN74ALVC244DWRG4	SN74ALVC244NSR	SN74ALVC244NSRE4	SN74ALVC244PW	SN74ALVC244PWE4	SN74ALVC244PWR	SN74ALVC244PWRE4	SN74ALVC244RGYR
Bits	8	8	8	8	8	8	8	8	8	8	8	8	8	8
F @ Nom Voltage(Max), Mhz	100	100	100	100	100	100	100	100	100	100	100	100	100	100
ICC @ Nom Voltage(Max), mA	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024	0.024
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24
Package Group	TVSOP	TVSOP	SOIC	SOIC	SOIC	SOIC	SOIC	SO	SO	TSSOP	TSSOP	TSSOP	TSSOP	VQFN
Package Size: mm2:W x L, PKG	20TVSOP: 32 mm2: 6.4 x 5(TVSOP)	20TVSOP: 32 mm2: 6.4 x 5(TVSOP)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SO: 98 mm2: 7.8 x 12.6(SO)	20SO: 98 mm2: 7.8 x 12.6(SO)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20VQFN: 16 mm2: 3.5 x 4.5(VQFN)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No	No	No	No	No	No
Technology Family	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65
Voltage(Nom), V	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8	4.4,3.1,2.8

Eco Plan

	SN74ALVC244DGVR	SN74ALVC244DGVRG4	SN74ALVC244DW	SN74ALVC244DWG4	SN74ALVC244DWR	SN74ALVC244DWRE4	SN74ALVC244DWRG4	SN74ALVC244NSR	SN74ALVC244NSRE4	SN74ALVC244PW	SN74ALVC244PWE4	SN74ALVC244PWR	SN74ALVC244PWRE4	SN74ALVC244RGYR
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

Application Notes

Download
TI SN74ALVC16835 Component Specification Analysis for PC100
PDF, 43 Kb, File published: Aug 3, 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
Download
Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
PDF, 96 Kb, Revision: A, File published: May 13, 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
Download
16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, Revision: B, File published: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
Download
Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
PDF, 154 Kb, Revision: A, File published: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

Model Line

Series: SN74ALVC244 (14)

SN74ALVC244DGVR SN74ALVC244DGVRG4 SN74ALVC244DW SN74ALVC244DWG4 SN74ALVC244DWR SN74ALVC244DWRE4 SN74ALVC244DWRG4 SN74ALVC244NSR SN74ALVC244NSRE4 SN74ALVC244PW SN74ALVC244PWE4 SN74ALVC244PWR SN74ALVC244PWRE4 SN74ALVC244RGYR

Manufacturer's Classification

Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver