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Datasheet Texas Instruments SN74LVT8986PM

Texas Instruments SN74LVT8986PM

Manufacturer:Texas Instruments
Series:SN74LVT8986
Part Number:SN74LVT8986PM

3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG) Tap Transceiver 64-LQFP -40 to 85

Datasheets

  • Download » Datasheet, PDF, 907 Kb, Revision: E, 05-14-2007
    3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG (Rev. E)

Prices

Family: SN54LVT8986, SN74LVT8986

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

Packaging

Pin64
Package TypePM
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingLVT8986
Width (mm)10
Length (mm)10
Thickness (mm)1.4
Pitch (mm).5
Max Height (mm)1.6
Mechanical DataDownload »

Parametrics

Approx. Price (US$)5.45 | 1ku
Operating Temperature Range(C)-40 to 85
Package GroupLQFP
Package Size: mm2:W x L (PKG)64LQFP: 144 mm2: 12 x 12(LQFP)
RatingCatalog
Technology FamilyLVT
VCC(Max)(V)3.6
VCC(Min)(V)2.7

Eco Plan

RoHSCompliant
Pb FreeYes

Manufacturer's Classification

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic

Application Notes

  • Download » Application Notes, PDF, 216 Kb, 11-05-2002
    Cascading Multiple Linking Addressable Scan Port Devices
    This application report is intended to illustrate the capability of cascading multiple Texas Instruments (TI) linking addressable scan port (LASP) devices. It explains configuring the secondary test access ports (TAPs) of cascaded LASPs with the help of a single linking shadow protocol and protocol-bypass inputs. Several examples of linking shadow protocol, along with timing requirements and scan
  • Download » Application Notes, PDF, 819 Kb, 11-01-2005
    Programming CPLDs Via the 'LVT8986 LASP
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • Download » Application Notes, PDF, 98 Kb, Revision: A, 03-01-1998
    LVT Family Characteristics (Rev. A)
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • Download » Application Notes, PDF, 84 Kb, 12-08-1998
    LVT-to-LVTH Conversion
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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