Multimedia Video Processor
PDF, 168 Kb, File published: Jul 1, 1997
This application report presents the preliminary results obtained in the realization of the MPEG2 video decoder on the Texas Instruments (TI(TM)) TM532OC80 MVP. We have addressed and solved the problems of bitstream scanning, variable-length code decoding, and inverse discrete cosine transform (DCT). The results obtained, integrated with preliminary work and available information about time requir
PDF, 446 Kb, File published: Feb 28, 1997
The TMS320C80 ('C80) is a 32-bit multiprocessor digital signal processor (DSP) that provides direct support of two independent frame memories through on-chip controllers. This document presents a 4M-byte video random access memory (VRAM) based frame buffer interface to the 'C80 DSP. An in-depth discussion of the hardware interface for the frame buffer card palette, a VRAM overview, and information
PDF, 135 Kb, File published: Jun 1, 1997
This report describes the coding requirements, techniques, and decisions whichmust be made to utilize the TMS320C80 DSP as an integrated services digitalnetwork (ISDN) video-system manager and provides an overview on how theprocessor handles video signal in the ISDN narrow-band format in conformancewith the International Telecommunications Union (ITU)?T H.261 Recommendation.
PDF, 270 Kb, File published: Jul 1, 1997
The coding of digital video sequences has been paid increasing attention over the past few years. Algorithms and standards such as MPEG1, MPEG2 or H.261 have been developed allowing more and more compression. A new standard in this field is H.263 which has been recently adopted by the ITU. It is intended for videoconferencing, videophoning, surveillance and other low bit rate applications (below 2
PDF, 98 Kb, File published: Mar 1, 1998
This application report describes the conversion of color-picture data from themacroblock (MB) format used by ITU-T Recommendation H.261 to the format usedby the Texas Instruments (TIE) TMS320C80 family of digital signal processors(DSPs). Conversion is necessary in some instances because of the differencebetween the MB format and the TI format and the necessity of the ?C80 to maintain co
PDF, 301 Kb, File published: Jul 1, 1996
The TMS320C80 ('C80) 32-bit multiprocessor digital signal processor (DSP) contains DRAM support in its memory interface. This document provides a DRAM functional description, describes the 'C80 address subcycles, and shows a DRAM system overview. The appendix provides a bill of materials, schematics, and ABEL files for this interface application.
PDF, 141 Kb, File published: Aug 1, 1996
This application report describes the implementation of the radix-4 decimation in frequency (DIF) fast Fourier transform (FFT) algorithm using the Texas Instruments (TI(TM)) TMS320C80 digital signal processor (DSP). The radix-4 DIF algorithm increases the execution speed of the FFT.Each TMS320C80 DSP parallel processor (PP) contains four major units operating in parallel. This parallel operati
PDF, 273 Kb, File published: Aug 1, 1996
The parallel architecture of the 32-bit multiprocessor TMS320C80 ('C80) digital signal processor (DSP) offers incredible horsepower that is underutilized without a high-speed memory interface. The 'C80 contains a built-in interface for SDRAM. This document discusses the interface between the 'C80 and the TMS626802-10 SDRAM, the SDRAM pins, and the SDRAM operation. A timing evaluation of the inter
PDF, 146 Kb, File published: Jul 1, 1997
This application report describes the process of parallelizing the scan conversion stage using the Texas Instruments (TI(TM)) TMS320C80 digital signal processor (DSP). Current approaches are discussed and a new approach is suggested to make the graphics pipeline faster, especially at the scan conversion stage. The suitability of the TMS320C80 for the suggested approach is investigated and the desi
PDF, 223 Kb, File published: May 1, 1996
Acoustic echo cancellation on the TMS320C8x multiprocessor digital signal processor (DSP) offers high performance and flexibility to meet varying user needs. This document describes the implementation of an integrated N-tap digital acoustic echo canceller on the TMS320C8x parallel processor (PP). A brief discussion of a generic echo cancellation algorithm is provided. A 512-tap (64-ms span) echo
PDF, 516 Kb, Revision: B, File published: Sep 1, 1995
The TMS320C8x is Texas Instruments? first generation of single-chipmultiprocessor digital signal processor (DSP) devices. Asingle ?C8x contains up to five powerful, fully programmable pro-cessors:a master processor (MP) and up to four parallel proces-sors(PPs). The MP is a 32-bit RISC (reduced instruction setcomputer) processor with an integral, high-performanceIEEE-754 floating-point
PDF, 101 Kb, File published: Jun 1, 1996
This document presents a modified Goertzel algorithm for DTMF tone detection on a TMS320C80 ('C80) 32-bit multiprocessor digital signal processor (DSP). The algorithm detects the incoming frequency with an offset range plus or minus 1.5%. For this application, a basic implementation is provided, but additional testing is required to make this detection algorithm complete. The appendix provides the
PDF, 40 Kb, File published: Jun 1, 1997
The TMS320 DSP C compilers produce several relocatable blocks of code and data when C code is compiled. These blocks are called sections and can be allocated into memory in a variety of ways to conform to a variety of system configurations. The .bss section is used by the compiler for global and static variables. It is one of the default COFF sections that is used to reserve a specified amount of
