Datasheet Texas Instruments TMS320DM8148

Manufacturer	Texas Instruments
Series	TMS320DM8148

Datasheets

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Status

Packaging

Parametrics

Parameters / Models	DVITDM8148CCYE1	HPSDM8148CCYE2	MTDM8148CCYE2	TDA1MDRCCYEA0	TMS320DM8148BCYE0	TMS320DM8148BCYE1	TMS320DM8148BCYE2	TMS320DM8148BCYE2F	TMS320DM8148CCYE0	TMS320DM8148CCYE1	TMS320DM8148CCYE2	TMS320DM8148CCYEA0	TMS320DM8148SCYE0	TMS320DM8148SCYE1	TMS320DM8148SCYE2	TMS320DM8148SCYEA0	TMX320DM8148BCYE
ARM CPU	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8	1 ARM Cortex-A8
ARM MHz, Max.	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000	1000
ARM MHz (Max.)																	1000
Applications	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security,Thin Client,Video Conferencing,Video Phones	Video Security Thin Client Video Conferencing Video Phones
Approx. Price (US$)																	43.95 | 1ku
DRAM	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR,DDR2,DDR3	LPDDR DDR2 DDR3
DSP	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x	1 C674x
DSP MHz, Max.	750	750	750	750	750	750	750	750	750	750	750	750	750	750	750	750
DSP MHz (Max.)																	750
EMAC	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000
I2C	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4
On-Chip L2 Cache	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM),256 KB (DSP)	512 KB (ARM) 256 KB (DSP)
Operating Systems	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux,DSP/BIOS	Linux DSP/BIOS
Operating Temperature Range(C)																	0 to 90
PCI/PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe	PCIe
Pin/Package	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA	684FCBGA
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
SPI	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4
UART, SCI	6	6	6	6	6	6	6	6	6	6	6	6	6	6	6	6
UART(SCI)																	6
USB	2	2	2	2	2	2	2	2	2	2	2	2	2	2	2	2	2
Video Acceleration	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP	1 HDVICP
Video Port, Configurable	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX	2 Output,2 Input,2 SD DACs,1 HDMI TX
Video Port (Configurable)																	2 Output 2 Input 2 SD DACs 1 HDMI TX
Video Resolution/Frame Rate	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p,60 FPS or less	1080p 60 FPS or less

Eco Plan

Application Notes

• Download
  TMS320DM814x/AM387x Power Estimation Spreadsheet (Rev. A)
  PDF, 18 Kb, Revision: A, File published: Sep 10, 2012
  This article describes how to model power consumption for a user's application and to present some measured power scenarios for the TMS320DM814x DaVinciв„ў digital media processors and AM387x Sitaraв„ў ARMВ® microprocessors (MPUs) PG2.x and PG3.x samples using a provided power estimation spreadsheet.This article has been contributed to the TI Developer Wiki. To see the most recen
• Download
  TI814x-DDR3-Init-U-Boot
  PDF, 37 Kb, File published: Oct 31, 2011
  This article describes how to initialize the DDR3 and uBoot on the TMS320DM814x DaVinciв„ў digital media processors (DSP) and AM387x ARMВ® microprocessors (MPUs) PG2.x samples using the software leveling process.This article has been contributed to the TI Embedded Processors Wiki. To see the most recently updated version or to contribute, visit this topic at:
• Download
  Canny Edge Detection Implementation on TMS320C64x/64x+ Using VLIB
  PDF, 97 Kb, File published: Nov 25, 2009
  This application note contains instructions for implementing Canny Edge Detection algorithm using VLIB. The general ideas given here can also be applied for an application which calls a sequence of VLIB functions in a block-based manner.
• Download
  Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
  PDF, 80 Kb, Revision: A, File published: Jul 19, 2013
  This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
• Download
  High-Speed Interface Layout Guidelines (Rev. G)
  PDF, 814 Kb, Revision: G, File published: Jul 27, 2017
  As modern bus interface frequencies scale higher, care must be taken in the printed circuit board (PCB) layout phase of a design to ensure a robust solution.
• Download
  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Kb, File published: Oct 6, 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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Manufacturer's Classification

• Semiconductors> Processors> Digital Signal Processors> Media Processors > DaVinci Video Processors