Datasheet Analog Devices AD641APZ

REVISIONS
LTR DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. -ro DESCRIPTION 02-03-18 R. MONNIN B Five year review requirement. -rrp 09-10-21 C. SAFFLE C Update drawings to current MIL-PRF-38535 requirements. -rrp 16-06-22 C. SAFFLE D Add device type 02. -ro 16-08-03 C. SAFFLE REV
SHEET
REV
SHEET
REV STATUS REV D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 PMIC N/A PREPARED BY
RICK OFFICER STANDARD
MICROCIRCUIT
DRAWING DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil CHECKED BY
RAJESH PITHADIA
APPROVED BY THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE AMSC N/A MICHAEL FRYE
DRAWING APPROVAL DATE MICROCIRCUIT, LINEAR, LOGARITHMIC
AMPLIFIER, MONOLITHIC SILICON 95-05-12
REVISION LEVEL
D SIZE CAGE CODE A 67268
SHEET DSCC FORM 2233
APR 97 5962-95598 …

PIN CONFIGURATIONS 20-Lead Plastic DIP (N)
20-Lead Cerdip (Q)
–INPUT 20
19 ATN OUT ATN COM 3 18 CKT COM ATN COM 4 17 RG1 ATN IN 5 16 RG0 AD641 TOP VIEW 15 RG2
(Not to Scale)
14 LOG OUT
–VS 7 BL1 6 ITC 8 13 BL2 9 12 +VS 11 +OUTPUT –OUTPUT 10 APPLICATIONS
IF/RF Signal Processing
Received Signal Strength Indicator (RSSI)
High Speed Signal Compression
High Speed Spectrum Analyzer
ECM/Radar –INPUT +INPUT ATN OUT 3 2 1 20 19 PIN 1
IDENTIFIER The AD641 is not a logarithmic building block, but rather a
complete logarithmic solution for compressing and measuring
wide dynamic range signals. The AD641 is comprised of five
stages and each stage has a full wave rectifier, whose current
depends on the absolute value of its input voltage. The output
of these stages are summed together to provide the demodulated
output current scaled at 1 mA per decade (50 µA/dB).
Without utilizing the 10× input attenuator, log conformance of
2.0 dB is maintained over the input range –44 dBm to 0 dBm.
The attenuator offers the most flexibility without significantly
impacting performance. ATN IN 5 18 CKT COM …

PIN CONFIGURATIONS 20-Lead Plastic DIP (N)
20-Lead Cerdip (Q)
–INPUT 20
19 ATN OUT ATN COM 3 18 CKT COM ATN COM 4 17 RG1 ATN IN 5 16 RG0 AD641 TOP VIEW 15 RG2
(Not to Scale)
14 LOG OUT
–VS 7 BL1 6 ITC 8 13 BL2 9 12 +VS 11 +OUTPUT –OUTPUT 10 APPLICATIONS
IF/RF Signal Processing
Received Signal Strength Indicator (RSSI)
High Speed Signal Compression
High Speed Spectrum Analyzer
ECM/Radar –INPUT +INPUT ATN OUT 3 2 1 20 19 PIN 1
IDENTIFIER The AD641 is not a logarithmic building block, but rather a
complete logarithmic solution for compressing and measuring
wide dynamic range signals. The AD641 is comprised of five
stages and each stage has a full wave rectifier, whose current
depends on the absolute value of its input voltage. The output
of these stages are summed together to provide the demodulated
output current scaled at 1 mA per decade (50 µA/dB).
Without utilizing the 10× input attenuator, log conformance of
2.0 dB is maintained over the input range –44 dBm to 0 dBm.
The attenuator offers the most flexibility without significantly
impacting performance. ATN IN 5 18 CKT COM …