Preliminary Datasheet ADP1074 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Isolated Synchronous Forward Controller with Active Clamp and iCoupler |
| Pages / Page | 14 / 5 — Preliminary Technical Data. ADP1074. Parameter. Symbol. Test … |
| File Format / Size | PDF / 380 Kb |
| Document Language | English |
Preliminary Technical Data. ADP1074. Parameter. Symbol. Test Conditions/Comments. Min. Typ. Max. Unit
Text Version of Document
Preliminary Technical Data ADP1074 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
GATE drivers (primary) NGATE and PGATE high voltage I = 20mA, VIN > 9V 7.6 8 8.4 V VREG1 Gate short circuit peak current1 8 V on VREG1 1.0 A NGATE Rise Time C = 2.2 nF, 10% to 90% 16 ns NGATE NGATE Fall Time C = 2.2 nF, 90% to 10% 16 ns NGATE PGATE Rise Time C = 410 pF, 10% to 90% 8 ns PGATE PGATE Fall Time C = 410 pF, 90% to 10% 8 ns PGATE NGATE R R Source 100mA 6 Ω ON ON_SOURCE NGATE R R Sink 100mA 4 Ω ON ON_SINK NGATE Max Duty Cycle D R = 0 Ω 45 50 55 % MAX BOT R = R , 1% resistors 75 % TOP BOT NGATE minimum on time At 300 kHz, includes blanking time 170 ns PGATE R R Source 100mA 10 Ω ON ON_SOURCE PGATE R R Sink 100mA 8 Ω ON ON_SINK SRx drivers (secondary) SR1 and SR2 high voltage I = 15mA, VDD2 > 5.5V 4.7 5 5.3 V VREG2 Gate short circuit peak current2 5 V on VREG2 1.0 A SRx Rise Time C = 2.2 nF, 10% to 90% 14 ns SRx SRx Fall Time C = 2.2 nF, 90% to 10% 11 ns SRx SRx minimum on time At 300 kHz 220 ns SR1, SR2 R R Source 100mA 6 Ω ON ON_SR_SOURCE R Sink 100mA 4 Ω ON_SR_SINK GATE Delay (SR1 rising to NGATE rising) 40 ns Delay between NGATE falling 14 ns edge and SR1 falling edge SR Dead time (PGATE rising to SR2 Resistor (±5%) at NGATE falling) R = 10 kΩ 150 ns DT R = 22 kΩ 100 ns DT R = 47 kΩ 60 ns DT R = open 30 ns DT SR1 and SR2 dead time Dead time between SR1 and SR2 25 ns CURRENT LIMIT SENSE (primary) CS limit threshold V Over current sense limit threshold 120 mV CS_LIM CS leading edge blanking time 150 ns Current source di/dt for slope compensation 20 µA/Ts OCP comparator delay Time in OCP before entering 20 ns hiccup mode 1.25 ms OCP hiccup time ms 45 FB PIN AND ERROR AMPLIFIER Feedback Accuracy Voltage V FB T = −40°C to +85°C −0.85% +1.2 +0.85% V J T = −40°C to +125°C −1.5% +1.2 +1.5% V J FB Input Bias Current -100 1 +100 nA Transconductance gm 212 250 287 μS Output current clamp minimum -65 μA Output current clamp maximum 40 μA Rev. PrB | Page 5 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS TYPICAL APPLICATION CIRCUITS SPECIFICATIONS REGULATORY INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SIMPLIFIED BLOCK DIAGRAM APPLICATIONS INFORMATION INSULATION LIFETIME OUTLINE DIMENSIONS
GATE drivers (primary) NGATE and PGATE high voltage I = 20mA, VIN > 9V 7.6 8 8.4 V VREG1 Gate short circuit peak current1 8 V on VREG1 1.0 A NGATE Rise Time C = 2.2 nF, 10% to 90% 16 ns NGATE NGATE Fall Time C = 2.2 nF, 90% to 10% 16 ns NGATE PGATE Rise Time C = 410 pF, 10% to 90% 8 ns PGATE PGATE Fall Time C = 410 pF, 90% to 10% 8 ns PGATE NGATE R R Source 100mA 6 Ω ON ON_SOURCE NGATE R R Sink 100mA 4 Ω ON ON_SINK NGATE Max Duty Cycle D R = 0 Ω 45 50 55 % MAX BOT R = R , 1% resistors 75 % TOP BOT NGATE minimum on time At 300 kHz, includes blanking time 170 ns PGATE R R Source 100mA 10 Ω ON ON_SOURCE PGATE R R Sink 100mA 8 Ω ON ON_SINK SRx drivers (secondary) SR1 and SR2 high voltage I = 15mA, VDD2 > 5.5V 4.7 5 5.3 V VREG2 Gate short circuit peak current2 5 V on VREG2 1.0 A SRx Rise Time C = 2.2 nF, 10% to 90% 14 ns SRx SRx Fall Time C = 2.2 nF, 90% to 10% 11 ns SRx SRx minimum on time At 300 kHz 220 ns SR1, SR2 R R Source 100mA 6 Ω ON ON_SR_SOURCE R Sink 100mA 4 Ω ON_SR_SINK GATE Delay (SR1 rising to NGATE rising) 40 ns Delay between NGATE falling 14 ns edge and SR1 falling edge SR Dead time (PGATE rising to SR2 Resistor (±5%) at NGATE falling) R = 10 kΩ 150 ns DT R = 22 kΩ 100 ns DT R = 47 kΩ 60 ns DT R = open 30 ns DT SR1 and SR2 dead time Dead time between SR1 and SR2 25 ns CURRENT LIMIT SENSE (primary) CS limit threshold V Over current sense limit threshold 120 mV CS_LIM CS leading edge blanking time 150 ns Current source di/dt for slope compensation 20 µA/Ts OCP comparator delay Time in OCP before entering 20 ns hiccup mode 1.25 ms OCP hiccup time ms 45 FB PIN AND ERROR AMPLIFIER Feedback Accuracy Voltage V FB T = −40°C to +85°C −0.85% +1.2 +0.85% V J T = −40°C to +125°C −1.5% +1.2 +1.5% V J FB Input Bias Current -100 1 +100 nA Transconductance gm 212 250 287 μS Output current clamp minimum -65 μA Output current clamp maximum 40 μA Rev. PrB | Page 5 of 14 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS TYPICAL APPLICATION CIRCUITS SPECIFICATIONS REGULATORY INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SIMPLIFIED BLOCK DIAGRAM APPLICATIONS INFORMATION INSULATION LIFETIME OUTLINE DIMENSIONS
