Datasheet AD7708, AD7718 (Analog Devices) - 2

ManufacturerAnalog Devices
Description24-Bit, 8/10-Channel, Low Voltage, Low Power, Sigma Delta ADC
Pages / Page44 / 2 — AD7708/AD7718. TABLE OF CONTENTS
File Format / SizePDF / 336 Kb
Document LanguageEnglish

AD7708/AD7718. TABLE OF CONTENTS

AD7708/AD7718 TABLE OF CONTENTS

Model Line for this Datasheet

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AD7708/AD7718 TABLE OF CONTENTS
FEATURES . 1 User Nonprogrammable Test Registers . 31 FUNCTIONAL BLOCK DIAGRAM . 1 Configuring the AD7708/AD7718 . 32 GENERAL DESCRIPTION . 1 DIGITAL INTERFACE . 34 AD7718 SPECIFICATIONS . 3 MICROCOMPUTER/MICROPROCESSOR AD7708 SPECIFICATIONS . 6 INTERFACING . 34 TIMING CHARACTERISTICS . 9 AD7708/AD7718 to 68HC11 Interface . 34 ABSOLUTE MAXIMUM RATINGS . 10 AD7708/AD7718-to-8051 Interface . 35 ORDERING GUIDE . 10 AD7708/AD7718-to-ADSP-2103/ADSP-2105 Interface . 36 PIN FUNCTION DESCRIPTIONS . 12 BASIC CONFIGURATION . 36 PIN CONFIGURATION . 13 Analog Input Channels . 37 ADC CIRCUIT INFORMATION . 15 Single-Ended Operation . 37 Signal Chain Overview (CHOP Enabled, CHOP = 0) . 15 Chop Mode of Operation (CHOP = 0) . 37 ADC NOISE PERFORMANCE CHOP ENABLED Nonchop Mode of Operation (CHOP = 1) . 38 (CHOP = 0) . 17 Programmable Gain Amplifier . 38 Signal Chain Overview (CHOP Disabled CHOP = 1) . 19 Bipolar/Unipolar Configuration . 38 ADC NOISE PERFORMANCE CHOP DISABLED Data Output Coding . 38 (CHOP = 1) . 20 Oscillator Circuit . 39 ON-CHIP REGISTERS . 22 Reference Input . 39 Communications Register . 25 RESET Input . 39 Status Register . 26 Power-Down Mode . 39 Mode Register . 27 Calibration . 40 Operating Characteristics when Addressing the Grounding and Layout . 40 Mode and Control Registers . 28 APPLICATIONS . 41 ADC Control Register . 28 Data Acquisition . 41 Filter Register . 29 Programmable Logic Controllers . 41 I/O Control Register . 30 Converting Single-Ended Inputs. 42 ADC Data Result Register . 30 Combined Ratiometric and Absolute Value Unipolar Mode . 30 Measurement System . 42 Bipolar Mode . 31 Optimizing Throughput while Maximizing 50 Hz ADC Offset Calibration Coefficient Registers . 31 and 60 Hz Rejection in a Multiplexed Data ADC Gain Calibration Coefficient Register . 31 Acquisition System . 43 ID Register (ID) . 31 OUTLINE DIMENSIONS . 44 –2– REV. 0
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