Datasheet MCP6141, MCP6142, MCP6143, MCP6144 (Microchip) - 9
| Manufacturer | Microchip |
| Description | The MCP6141 is a single 600 nA op amp offering rail-to-rail input & output over the 1.4 to 5.5V operating range |
| Pages / Page | 38 / 9 — MCP6141/2/3/4. Note:. 10000. 10k. VDD = 5.5V. rren. CM = VDD. 1000. rre. … |
| File Format / Size | PDF / 649 Kb |
| Document Language | English |
MCP6141/2/3/4. Note:. 10000. 10k. VDD = 5.5V. rren. CM = VDD. 1000. rre. set. A = +125°C. 100. nd Off. , Of. ias. | I. A = +85°C. OS |. t B. Bias. p In. Input. 0.1
Model Line for this Datasheet
- MCP6141-E/MS MCP6141-E/P MCP6141-E/SN MCP6141-E/SNVAO MCP6141-I/MS MCP6141-I/P MCP6141-I/SN MCP6141T-E/MS MCP6141T-E/OT MCP6141T-E/OTVAO MCP6141T-E/SN MCP6141T-I/MS MCP6141T-I/SN
- MCP6142-E/MS MCP6142-E/MSVAO MCP6142-E/P MCP6142-E/SN MCP6142-I/MS MCP6142-I/P MCP6142-I/SN MCP6142T-E/MS MCP6142T-E/MSVAO MCP6142T-E/SN MCP6142T-I/MS MCP6142T-I/SN
Text Version of Document
MCP6141/2/3/4 Note:
Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low.
10000 10k 10000 10k ts VDD = 5.5V VDD = 5.5V V ts rren CM = VDD n 1000 u 1k 1000 rre 1k C Cu IB T set A = +125°C 100 10 et 100 100 A) IB fs A) (p (p nd Off 10 , Of 10 a ias T | I A = +85°C OS | | I t B Bias 1 OS | 1 u 1 p In Input 0.1 0.1 0.1 0.1 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents vs. Ambient Temperature. vs. Common Mode Input Voltage.
120 0 130 100 -30 120 B) °) d 80 -60 ( Phase se 110 VDD = 5.5V 60 -90 100 p Gain ( 40 -120 Gain oop Pha V 90 DD = 1.4V 20 -Loo -150 -L n n 0 -180 80 Ope Ope Open-Loop Gain (dB) -20 -210 C 70 D VOUT = 0.1V to VDD – 0.1V -40 -240 60 1. 0.E- 01 1.0E.-1 1.E1+ 1.E 1 + 0 1.E 10 + 0 1.E 1k+ 1.E 1 + 0k 1.E 1 + 00k 1.E 1 +002 0 1.E+ 1 0 k 3 1.E 1 +04 0k 1.E+ 10 05 0k 02 01 00 Fr 01 eque 02 ncy (H 03 z) 04 05 Load Resistance (Ω) FIGURE 2-14:
Open-Loop Gain, Phase vs.
FIGURE 2-17:
DC Open-Loop Gain vs. Frequency. Load Resistance.
140 140 B) RL = 50 kΩ 130 d 130 120 VDD = 5.5V 120 110 110 Loop Gain ( 100 VDD = 1.4V 100 90 80 90 RL = 50 kΩ DC Open- DC Open-Loop Gain (dB) V 70 OUT = 0.1V to VDD – 0.1V 80 0.00 0.05 0.10 0.15 0.20 0.25 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD – VOH or VOL – VSS (V) FIGURE 2-15:
DC Open-Loop Gain vs.
FIGURE 2-18:
DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom. © 2009 Microchip Technology Inc. DS21668D-page 9 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). FIGURE 2-33: Input Current vs. Input Voltage (Below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 CS Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Stability FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration. FIGURE 4-4: Noise Gain for Inverting Gain Configuration. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-7: Recommended RISO Values for Capacitive Loads. 4.5 MCP6143 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-8: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-9: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-10: High Side Battery Current Sensor. FIGURE 4-11: Summing Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulation Tool 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
Unless otherwise indicated, TA = +25°C, VDD = +1.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF, and CS is tied low.
10000 10k 10000 10k ts VDD = 5.5V VDD = 5.5V V ts rren CM = VDD n 1000 u 1k 1000 rre 1k C Cu IB T set A = +125°C 100 10 et 100 100 A) IB fs A) (p (p nd Off 10 , Of 10 a ias T | I A = +85°C OS | | I t B Bias 1 OS | 1 u 1 p In Input 0.1 0.1 0.1 0.1 45 55 65 75 85 95 105 115 125 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Ambient Temperature (°C) Common Mode Input Voltage (V) FIGURE 2-13:
Input Bias, Offset Currents
FIGURE 2-16:
Input Bias, Offset Currents vs. Ambient Temperature. vs. Common Mode Input Voltage.
120 0 130 100 -30 120 B) °) d 80 -60 ( Phase se 110 VDD = 5.5V 60 -90 100 p Gain ( 40 -120 Gain oop Pha V 90 DD = 1.4V 20 -Loo -150 -L n n 0 -180 80 Ope Ope Open-Loop Gain (dB) -20 -210 C 70 D VOUT = 0.1V to VDD – 0.1V -40 -240 60 1. 0.E- 01 1.0E.-1 1.E1+ 1.E 1 + 0 1.E 10 + 0 1.E 1k+ 1.E 1 + 0k 1.E 1 + 00k 1.E 1 +002 0 1.E+ 1 0 k 3 1.E 1 +04 0k 1.E+ 10 05 0k 02 01 00 Fr 01 eque 02 ncy (H 03 z) 04 05 Load Resistance (Ω) FIGURE 2-14:
Open-Loop Gain, Phase vs.
FIGURE 2-17:
DC Open-Loop Gain vs. Frequency. Load Resistance.
140 140 B) RL = 50 kΩ 130 d 130 120 VDD = 5.5V 120 110 110 Loop Gain ( 100 VDD = 1.4V 100 90 80 90 RL = 50 kΩ DC Open- DC Open-Loop Gain (dB) V 70 OUT = 0.1V to VDD – 0.1V 80 0.00 0.05 0.10 0.15 0.20 0.25 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage Headroom; Power Supply Voltage (V) VDD – VOH or VOL – VSS (V) FIGURE 2-15:
DC Open-Loop Gain vs.
FIGURE 2-18:
DC Open-Loop Gain vs. Power Supply Voltage. Output Voltage Headroom. © 2009 Microchip Technology Inc. DS21668D-page 9 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Chip Select (CS) Timing Diagram (MCP6143 only). 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift with TA = -40°C to +85°C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.4V. FIGURE 2-4: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 1.4V. FIGURE 2-5: Input Offset Voltage Drift with TA = +85°C to +125°C and VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: CMRR, PSRR vs. Frequency. FIGURE 2-10: The MCP6141/2/3/4 Family Shows No Phase Reversal. FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-12: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-16: Input Bias, Offset Currents vs. Common Mode Input Voltage. FIGURE 2-17: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel to Channel Separation vs. Frequency (MCP6142 and MCP6144 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 1.4V. FIGURE 2-21: Quiescent Current vs. Power Supply Voltage. FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-24: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-25: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-inverting Pulse Response. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small Signal Inverting Pulse Response. FIGURE 2-31: Large Signal Non-inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP6143 only). FIGURE 2-33: Input Current vs. Input Voltage (Below VSS). FIGURE 2-34: Large Signal Inverting Pulse Response. FIGURE 2-35: Internal Chip Select (CS) Hysteresis (MCP6143 only). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 CS Digital Input 3.4 Power Supply Pins 4.0 Applications Information 4.1 Rail-to-Rail Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Output Loads and Battery Life 4.4 Stability FIGURE 4-3: Noise Gain for Non-inverting Gain Configuration. FIGURE 4-4: Noise Gain for Inverting Gain Configuration. FIGURE 4-5: Examples of Unstable Circuits for the MCP6141/2/3/4 Family. FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-7: Recommended RISO Values for Capacitive Loads. 4.5 MCP6143 Chip Select 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-8: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-9: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-10: High Side Battery Current Sensor. FIGURE 4-11: Summing Amplifier. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulation Tool 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
