Datasheet LTC1407-1, LTC1407A-1 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown |
| Pages / Page | 26 / 5 — TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over … |
| File Format / Size | PDF / 520 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifi cations which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC1407-1/LTC1407A-1
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel l 1.5 MHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l 667 ns tSCK Clock Period (Note 16) l 19.6 10000 ns tCONV Conversion Time (Note 6) 32 34 SCLK cycles t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns t3 SCK Before CONV (Note 6) 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns t5 SCK to Sample Mode (Note 6) 4 ns t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns t7 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliability and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 2:
All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3:
When these pins are taken below GND or above V 1.2ns CONV to hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+
Note 13:
The time period for acquiring the input signal is started by the or CH1+ input with CH0– or CH1– grounded and using the internal 2.5V 32nd rising clock and it is ended by the rising edge of CONV. reference.
Note 14:
The internal reference settles in 2ms after it wakes up from sleep
Note 5:
Integral linearity is tested with an external 2.55V reference and is mode with one or more cycles at SCK and a 10μF capacitive load. defi ned as the deviation of a code from the straight line passing through
Note 15:
The full power bandwidth is the frequency where the output code the actual endpoints of a transfer curve. The deviation is measured from swing drops by 3dB with a 2.5VP-P input sine wave. the center of quantization band.
Note 16:
Maximum clock period guarantees analog performance during
Note 6:
Guaranteed by design, not subject to test. conversion. Output data can be read with an arbitrarily long clock period.
Note 7:
Recommended operating conditions.
Note 17:
The LTC1407A-1 is measured and specifi ed with 14-bit
Note 8:
The analog input range is defi ned for the voltage difference Resolution (1LSB = 152μV) and the LTC1407-1 is measured and specifi ed between CH0+ and CH0– or CH1+ and CH1–. Performance is specifi ed with 12-bit Resolution (1LSB = 610μV). with CHO– = 1.5V DC while driving CHO+ and with CH1– = 1.5V DC while
Note 18:
The sampling capacitor at each input accounts for 4.1pF of the driving CH1+. input capacitance.
Note 9:
The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be
Note 19:
Full-scale sinewaves are fed into the noninverting inputs while within this range. the inverting inputs are kept at 1.5V DC. 14071fb 5
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel l 1.5 MHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l 667 ns tSCK Clock Period (Note 16) l 19.6 10000 ns tCONV Conversion Time (Note 6) 32 34 SCLK cycles t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns t3 SCK Before CONV (Note 6) 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns t5 SCK to Sample Mode (Note 6) 4 ns t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns t7 32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 6, 12) 8 ns t9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 10:
If less than 3ns is allowed, the output data will appear one may cause permanent damage to the device. Exposure to any Absolute clock cycle later. It is best for CONV to rise half a clock before SCK, when Maximum Rating condition for extended periods may affect device running the clock at rated speed. reliability and lifetime.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
Note 2:
All voltage values are with respect to ground GND. difference between the 2.2ns delay through the sample-and-hold and the
Note 3:
When these pins are taken below GND or above V 1.2ns CONV to hold mode delay. DD, they will be clamped by internal diodes. This product can handle input currents greater
Note 12:
The rising edge of SCK is guaranteed to catch the data coming than 100mA below GND or greater than VDD without latchup. out into a storage latch.
Note 4:
Offset and range specifi cations apply for a single-ended CH0+
Note 13:
The time period for acquiring the input signal is started by the or CH1+ input with CH0– or CH1– grounded and using the internal 2.5V 32nd rising clock and it is ended by the rising edge of CONV. reference.
Note 14:
The internal reference settles in 2ms after it wakes up from sleep
Note 5:
Integral linearity is tested with an external 2.55V reference and is mode with one or more cycles at SCK and a 10μF capacitive load. defi ned as the deviation of a code from the straight line passing through
Note 15:
The full power bandwidth is the frequency where the output code the actual endpoints of a transfer curve. The deviation is measured from swing drops by 3dB with a 2.5VP-P input sine wave. the center of quantization band.
Note 16:
Maximum clock period guarantees analog performance during
Note 6:
Guaranteed by design, not subject to test. conversion. Output data can be read with an arbitrarily long clock period.
Note 7:
Recommended operating conditions.
Note 17:
The LTC1407A-1 is measured and specifi ed with 14-bit
Note 8:
The analog input range is defi ned for the voltage difference Resolution (1LSB = 152μV) and the LTC1407-1 is measured and specifi ed between CH0+ and CH0– or CH1+ and CH1–. Performance is specifi ed with 12-bit Resolution (1LSB = 610μV). with CHO– = 1.5V DC while driving CHO+ and with CH1– = 1.5V DC while
Note 18:
The sampling capacitor at each input accounts for 4.1pF of the driving CH1+. input capacitance.
Note 9:
The absolute voltage at CH0+, CH0–, CH1+ and CH1– must be
Note 19:
Full-scale sinewaves are fed into the noninverting inputs while within this range. the inverting inputs are kept at 1.5V DC. 14071fb 5
