Datasheet LTC1410 (Analog Devices) - 4

LTC1410
W U POWER REQUIRE E TS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PD Power Dissipation 160 230 mW Nap Mode SHDN = 0V, NAP/SLP = 5V 7.5 12 mW Sleep Mode SHDN = 0V, NAP/SLP = 0V 0.01 1 mW
W U TI I G CHARACTERISTICS The
●
denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 1.25 MHz tCONV Conversion Time ● 650 750 ns tACQ Acquisition Time ● 50 100 ns tACQ+CONV Throughput Time ● 800 ns (Acquisition + Conversion) t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 NAP/SLP↓ to SHDN↓ Setup Time (Notes 9, 10) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time (Note 10) 200 ns t5 CONVST Low Time (Notes 10, 11) ● 40 ns t6 CONVST to BUSY Delay CL = 25pF 10 ns ● 50 ns t7 Data Ready Before BUSY↑ 20 35 ns ● 15 ns t8 Delay Between Conversions (Note 10) ● 40 ns t9 Wait Time RD↓ After BUSY↑ (Note 10) ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 15 25 ns ● 35 ns CL = 100pF 20 35 ns ● 50 ns t11 Bus Relinquish Time 8 20 ns Commercial ● 25 ns Industrial ● 30 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 40 ns t14 Aperture Delay of Sample-and-Hold – 1.5 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 2:
All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted.
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 3:
When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents
Note 9:
Guaranteed by design, not subject to test. greater than 100mA below VSS or above VDD without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below VSS, they will be clamped
Note 11:
The falling CONVST edge starts a conversion. If CONVST returns by internal diodes. This product can handle input currents greater than high at a critical point during the conversion it can create small errors. For 100mA below VSS without latchup. These pins are not clamped to VDD. best results ensure that CONVST returns high either within 425ns after the
Note 5:
V start of the conversion or after BUSY rises. DD = 5V, VSS = – 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise specified.
Note 12:
Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
Note 6:
Linearity, offset and full-scale specifications apply for a single- is measured at 600kHz. These results are used to calculate signal-to-noise ended +A plus distortion (SINAD). IN input with – AIN grounded. 4