Datasheet LTC1417 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O |
| Pages / Page | 32 / 4 — POWER REQUIRE E TS The. indicates specifications which apply over the … |
| File Format / Size | PDF / 413 Kb |
| Document Language | English |
POWER REQUIRE E TS The. indicates specifications which apply over the full operating temperature range,
Model Line for this Datasheet
Text Version of Document
LTC1417
W U POWER REQUIRE E TS The
●
indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage (Notes 10, 11) 4.75 5.25 V VSS Negative Supply Voltage (Note 10) Bipolar Only (VSS = 0V for Unipolar) – 4.75 – 5.25 V IDD Positive Supply Current Unipolar, RD High (Note 5) ● 4.0 5.5 mA Bipolar, RD High (Note 5) ● 4.3 6.0 mA Nap Mode SHDN = 0V, RD = 0V 750 µA Sleep Mode SHDN = 0V, RD = 5V 0.1 µA ISS Negative Supply Current Bipolar, RD High (Note 5) ● 2.0 2.8 mA Nap Mode SHDN = 0V, RD = 0V 0.7 µA Sleep Mode SHDN = 0V, RD = 5V 1.5 nA PDIS Power Dissipation Unipolar ● 20.0 27.5 mW Bipolar ● 31.5 44 mW
W U TI I G CHARACTERISTICS The
●
indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 400 kHz tCONV Conversion Time ● 1.8 2.25 µs tACQ Acquisition Time ● 150 500 ns tACQ + tCONV Acquisition Plus Conversion Time ● 2.1 2.5 µs t1 SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode (Note 10) 500 ns t2 CONVST Low Time (Notes 10, 11) ● 40 ns t3 CONVST to BUSY Delay CL = 25pF ● 35 70 ns t4 Data Ready Before BUSY↑ CL = 25pF ● 7 12 ns t5 Delay Between Conversions (Note 10) ● 250 ns t6 Wait Time RD↓ After BUSY↑ ● – 5 ns t7 Data Access Time After RD↓ CL = 25pF 15 30 ns ● 40 ns CL = 100pF 20 40 ns ● 55 ns t8 Bus Relinquish Time ● 35 ns t9 RD Low Time ● t7 ns t10 CONVST High Time ● 40 ns t11 Delay Time, SCLK↓ to DOUT Valid CL = 25pF ● 15 40 ns t12 Time from Previous Data Remain Valid After SCLK↓ CL = 25pF ● 5 10 ns fSCLK Shift Clock Frequency (Note 13) ● 0 20 MHz fEXTCLKIN External Conversion Clock Frequency ● 0.05 9 MHz tdEXTCLKIN Delay Time, CONVST↓ to External Conversion Clock Input (Note 9) ● 20 µs sn1417 1417fas 4
W U POWER REQUIRE E TS The
●
indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage (Notes 10, 11) 4.75 5.25 V VSS Negative Supply Voltage (Note 10) Bipolar Only (VSS = 0V for Unipolar) – 4.75 – 5.25 V IDD Positive Supply Current Unipolar, RD High (Note 5) ● 4.0 5.5 mA Bipolar, RD High (Note 5) ● 4.3 6.0 mA Nap Mode SHDN = 0V, RD = 0V 750 µA Sleep Mode SHDN = 0V, RD = 5V 0.1 µA ISS Negative Supply Current Bipolar, RD High (Note 5) ● 2.0 2.8 mA Nap Mode SHDN = 0V, RD = 0V 0.7 µA Sleep Mode SHDN = 0V, RD = 5V 1.5 nA PDIS Power Dissipation Unipolar ● 20.0 27.5 mW Bipolar ● 31.5 44 mW
W U TI I G CHARACTERISTICS The
●
indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 400 kHz tCONV Conversion Time ● 1.8 2.25 µs tACQ Acquisition Time ● 150 500 ns tACQ + tCONV Acquisition Plus Conversion Time ● 2.1 2.5 µs t1 SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode (Note 10) 500 ns t2 CONVST Low Time (Notes 10, 11) ● 40 ns t3 CONVST to BUSY Delay CL = 25pF ● 35 70 ns t4 Data Ready Before BUSY↑ CL = 25pF ● 7 12 ns t5 Delay Between Conversions (Note 10) ● 250 ns t6 Wait Time RD↓ After BUSY↑ ● – 5 ns t7 Data Access Time After RD↓ CL = 25pF 15 30 ns ● 40 ns CL = 100pF 20 40 ns ● 55 ns t8 Bus Relinquish Time ● 35 ns t9 RD Low Time ● t7 ns t10 CONVST High Time ● 40 ns t11 Delay Time, SCLK↓ to DOUT Valid CL = 25pF ● 15 40 ns t12 Time from Previous Data Remain Valid After SCLK↓ CL = 25pF ● 5 10 ns fSCLK Shift Clock Frequency (Note 13) ● 0 20 MHz fEXTCLKIN External Conversion Clock Frequency ● 0.05 9 MHz tdEXTCLKIN Delay Time, CONVST↓ to External Conversion Clock Input (Note 9) ● 20 µs sn1417 1417fas 4
