Datasheet LTC1418 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O |
| Pages / Page | 30 / 5 — TIMING CHARACTERISTICS. The. denotes the specifications which apply over … |
| File Format / Size | PDF / 486 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC1418
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency l 200 kHz tCONV Conversion Time l 3.4 4 µs tACQ Acquisition Time l 0.3 1 µs tACQ + tCONV Acquisition Plus Conversion Time l 3.7 5 µs t1 CS to RD Setup Time (Notes 9, 10) l 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) l 40 ns t3 CS↓ to SHDN↓ Setup Time to Ensure Nap Mode (Notes 9, 10) l 40 ns t4 SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode (Note 10) 500 ns t5 CONVST Low Time (Notes 10, 11) l 40 ns t6 CONVST to BUSY Delay CL = 25pF l 35 70 ns t7 Data Ready Before BUSY↑ 20 35 ns l 15 ns t8 Delay Between Conversions (Note 10) l 500 ns t9 Wait Time RD↓ After BUSY↑ l –5 ns t10 Data Access Time After RD↓ CL = 25pF 15 30 ns l 40 ns CL = 100pF 20 40 ns l 55 ns t11 Bus Relinquish Time 8 20 ns Commercial l 25 ns Industrial l 30 ns t12 RD Low Time l t10 ns t13 CONVST High Time 40 ns t14 Delay Time, SCLK↓ to DOUT Valid CL = 25pF (Note 9) l 35 70 ns t15 Time from Previous Data Remain Valid After SCLK↓ CL = 25pF (Note 9) l 15 25 ns fSCLK Shift Clock Frequency (Notes 9, 10) 0 12.5 MHz fEXTCLKIN External Conversion Clock Frequency (Notes 9, 10) 0.03 4.5 MHz tdEXTCLKIN Delay Time, CONVST↓ to External Conversion Clock Input (Notes 9, 10) 533 µs tH SCLK SCLK High Time (Notes 9, 10) 10 ns tL SCLK SCLK Low Time (Notes 9, 10) 20 ns tH EXTCLKIN EXTCLKIN High Time (Notes 9, 10) 250 ns tL EXTCLKIN EXTCLKIN Low Time (Notes 9, 10) 250 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Linearity, offset and full-scale specifications apply for a single- may cause permanent damage to the device. Exposure to any Absolute ended input with A – IN grounded. Maximum Rating condition for extended periods may affect device
Note 7:
Integral nonlinearity is defined as the deviation of a code from a reliability and lifetime. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND and The deviation is measured from the center of the quantization band. AGND wired together (unless otherwise noted).
Note 8:
Bipolar offset is the offset voltage measured from –0.5LSB when the
Note 3:
When these pin voltages are taken below VSS or above VDD, they output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. will be clamped by internal diodes. This product can handle input currents
Note 9:
Guaranteed by design, not subject to test. greater than 100mA below VSS or above VCC without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below VSS they will be clamped
Note 11:
The falling edge of CONVST starts a conversion. If CONVST by internal diodes. This product can handle input currents greater than returns high at a critical point during the conversion, it can create small 100mA below VSS without latchup. These pins are not clamped to VDD. errors. For best performance ensure that CONVST returns high either
Note 5:
VDD = 5V, VSS = 0V or –5V, fSAMPLE = 200kHz, tr = tf = 5ns unless within 2.1µs after the conversion starts or after BUSY rises. otherwise specified.
Note 12:
Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at 0V or 5V. See Power Shutdown. 1418fa For more information www.linear.com/LTC1418 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Package/Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Test Circuit Block Diagram Applications Information Package Description Package Description Revision History Typical Application Related Parts
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency l 200 kHz tCONV Conversion Time l 3.4 4 µs tACQ Acquisition Time l 0.3 1 µs tACQ + tCONV Acquisition Plus Conversion Time l 3.7 5 µs t1 CS to RD Setup Time (Notes 9, 10) l 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) l 40 ns t3 CS↓ to SHDN↓ Setup Time to Ensure Nap Mode (Notes 9, 10) l 40 ns t4 SHDN↑ to CONVST↓ Wake-Up Time from Nap Mode (Note 10) 500 ns t5 CONVST Low Time (Notes 10, 11) l 40 ns t6 CONVST to BUSY Delay CL = 25pF l 35 70 ns t7 Data Ready Before BUSY↑ 20 35 ns l 15 ns t8 Delay Between Conversions (Note 10) l 500 ns t9 Wait Time RD↓ After BUSY↑ l –5 ns t10 Data Access Time After RD↓ CL = 25pF 15 30 ns l 40 ns CL = 100pF 20 40 ns l 55 ns t11 Bus Relinquish Time 8 20 ns Commercial l 25 ns Industrial l 30 ns t12 RD Low Time l t10 ns t13 CONVST High Time 40 ns t14 Delay Time, SCLK↓ to DOUT Valid CL = 25pF (Note 9) l 35 70 ns t15 Time from Previous Data Remain Valid After SCLK↓ CL = 25pF (Note 9) l 15 25 ns fSCLK Shift Clock Frequency (Notes 9, 10) 0 12.5 MHz fEXTCLKIN External Conversion Clock Frequency (Notes 9, 10) 0.03 4.5 MHz tdEXTCLKIN Delay Time, CONVST↓ to External Conversion Clock Input (Notes 9, 10) 533 µs tH SCLK SCLK High Time (Notes 9, 10) 10 ns tL SCLK SCLK Low Time (Notes 9, 10) 20 ns tH EXTCLKIN EXTCLKIN High Time (Notes 9, 10) 250 ns tL EXTCLKIN EXTCLKIN Low Time (Notes 9, 10) 250 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Linearity, offset and full-scale specifications apply for a single- may cause permanent damage to the device. Exposure to any Absolute ended input with A – IN grounded. Maximum Rating condition for extended periods may affect device
Note 7:
Integral nonlinearity is defined as the deviation of a code from a reliability and lifetime. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND and The deviation is measured from the center of the quantization band. AGND wired together (unless otherwise noted).
Note 8:
Bipolar offset is the offset voltage measured from –0.5LSB when the
Note 3:
When these pin voltages are taken below VSS or above VDD, they output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. will be clamped by internal diodes. This product can handle input currents
Note 9:
Guaranteed by design, not subject to test. greater than 100mA below VSS or above VCC without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below VSS they will be clamped
Note 11:
The falling edge of CONVST starts a conversion. If CONVST by internal diodes. This product can handle input currents greater than returns high at a critical point during the conversion, it can create small 100mA below VSS without latchup. These pins are not clamped to VDD. errors. For best performance ensure that CONVST returns high either
Note 5:
VDD = 5V, VSS = 0V or –5V, fSAMPLE = 200kHz, tr = tf = 5ns unless within 2.1µs after the conversion starts or after BUSY rises. otherwise specified.
Note 12:
Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at 0V or 5V. See Power Shutdown. 1418fa For more information www.linear.com/LTC1418 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Package/Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Test Circuit Block Diagram Applications Information Package Description Package Description Revision History Typical Application Related Parts
