Datasheet LTC2309 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 8-Channel, 12-Bit SAR ADC with I2C Interface |
| Pages / Page | 26 / 4 — The. denotes the specifications which apply over the full |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
The. denotes the specifications which apply over the full
Model Line for this Datasheet
- LTC2309CF#PBF LTC2309CF#PBF LTC2309CF#TRPBF LTC2309CF#TRPBF LTC2309CUF#PBF LTC2309CUF#PBF LTC2309CUF#TRPBF LTC2309CUF#TRPBF LTC2309HF#PBF LTC2309HF#PBF LTC2309HF#TRPBF LTC2309HF#TRPBF LTC2309IF#PBF LTC2309IF#PBF LTC2309IF#TRPBF LTC2309IF#TRPBF LTC2309IUF#PBF LTC2309IUF#PBF LTC2309IUF#TRPBF LTC2309IUF#TRPBF
Text Version of Document
LTC2309 I
nteRnAL ReFeRenCe CHARACteRIstICs
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 (QFN) l 2.47 2.50 2.53 V IOUT = 0 (TSSOP) l 2.46 2.50 2.54 V VREF Output Tempco IOUT = 0 ±25 ppm/°C VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ VREFCOMP Output Voltage IOUT = 0 4.096 V VREF Line Regulation VDD = 4.75V to 5.25V 0.8 mV/V I2
C Inputs AnD DIGItAL Outputs
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 2.85 V VIL Low Level Input Voltage l 1.5 V VIHA High Level Input Voltage for Address Pins A1, A0 l 4.75 V VILA Low Level Input Voltage for Address Pins A1, A0 l 0.25 V RINH Resistance from A1, A0, to VDD to Set Chip l 10 kΩ Address Bit to 1 RINL Resistance from A1, A0 to GND to Set Chip l 10 kΩ Address Bit to 0 RINF Resistance from A1, A0 to GND or VDD to Set l 2 MΩ Chip Address Bit to Float II Digital Input Current VIN = VDD l –10 10 µA VHYS Hysteresis of Schmitt Trigger Inputs (Note 9) l 0.25 V VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V tOF Output Fall Time VH to VIL(MAX) (Note 12) l 20 + 0.1CB 250 ns tSP Input Spike Suppression l 50 ns CCAX External Capacitance Load On-Chip Address Pins l 10 pF (A1, A0) for Valid Float p
OWeR ReQuIReMents
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 4.75 5 5.25 V IDD Supply Current 14ksps Sample Rate l 2.3 3 mA Nap Mode SLP Bit = 0, Conversion Done l 210 350 µA Sleep Mode SLP Bit = 1, Conversion Done l 7 15 µA PD Power Dissipation 14ksps Sample Rate l 11.5 15 mW Nap Mode SLP Bit = 0, Conversion Done l 1.05 1.75 mW Sleep Mode SLP Bit = 1, Conversion Done l 35 75 µW 2309fd Document Outline Features Description Applications Absolute Maximum Ratings Pin Configuration Order Information CONVERTER AND MULTIPLEXER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS I2C Inputs and Digital Outputs POWER REQUIREMENTS I2C TIMING CHARACTERISTICS ADC TIMING CHARACTERISTICS Typical Performance Characteristics Pin Functions Functional Block Diagram TIMING DIAGRAM Applications Information Package Description Revision History Typical Application Related Parts
nteRnAL ReFeRenCe CHARACteRIstICs
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN TYP MAX UNITS
VREF Output Voltage IOUT = 0 (QFN) l 2.47 2.50 2.53 V IOUT = 0 (TSSOP) l 2.46 2.50 2.54 V VREF Output Tempco IOUT = 0 ±25 ppm/°C VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 8 kΩ VREFCOMP Output Voltage IOUT = 0 4.096 V VREF Line Regulation VDD = 4.75V to 5.25V 0.8 mV/V I2
C Inputs AnD DIGItAL Outputs
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l 2.85 V VIL Low Level Input Voltage l 1.5 V VIHA High Level Input Voltage for Address Pins A1, A0 l 4.75 V VILA Low Level Input Voltage for Address Pins A1, A0 l 0.25 V RINH Resistance from A1, A0, to VDD to Set Chip l 10 kΩ Address Bit to 1 RINL Resistance from A1, A0 to GND to Set Chip l 10 kΩ Address Bit to 0 RINF Resistance from A1, A0 to GND or VDD to Set l 2 MΩ Chip Address Bit to Float II Digital Input Current VIN = VDD l –10 10 µA VHYS Hysteresis of Schmitt Trigger Inputs (Note 9) l 0.25 V VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V tOF Output Fall Time VH to VIL(MAX) (Note 12) l 20 + 0.1CB 250 ns tSP Input Spike Suppression l 50 ns CCAX External Capacitance Load On-Chip Address Pins l 10 pF (A1, A0) for Valid Float p
OWeR ReQuIReMents
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l 4.75 5 5.25 V IDD Supply Current 14ksps Sample Rate l 2.3 3 mA Nap Mode SLP Bit = 0, Conversion Done l 210 350 µA Sleep Mode SLP Bit = 1, Conversion Done l 7 15 µA PD Power Dissipation 14ksps Sample Rate l 11.5 15 mW Nap Mode SLP Bit = 0, Conversion Done l 1.05 1.75 mW Sleep Mode SLP Bit = 1, Conversion Done l 35 75 µW 2309fd Document Outline Features Description Applications Absolute Maximum Ratings Pin Configuration Order Information CONVERTER AND MULTIPLEXER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS I2C Inputs and Digital Outputs POWER REQUIREMENTS I2C TIMING CHARACTERISTICS ADC TIMING CHARACTERISTICS Typical Performance Characteristics Pin Functions Functional Block Diagram TIMING DIAGRAM Applications Information Package Description Revision History Typical Application Related Parts
