Datasheet LTC2356-12, LTC2356-14 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Serial 14-Bit, 3.5Msps Sampling ADC with Bipolar inputs |
| Pages / Page | 20 / 5 — timing characteristics. The. denotes the specifications which apply over … |
| File Format / Size | PDF / 531 Kb |
| Document Language | English |
timing characteristics. The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2356-12/LTC2356-14
timing characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Rate per Channel l 3.5 MHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l 286 ns tSCK Clock Period (Note 16) l 15.872 10000 ns tCONV Conversion Time (Note 6) 17 18 SCLK cycles t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV≠ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Delay from SCK to Valid Data (Notes 6, 12) 8 ns t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Note 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns) may cause permanent damage to the device. Exposure to any Absolute because the 2.2ns delay through the sample-and-hold is subtracted from Maximum Rating condition for extended periods may affect device the CONV to Hold mode delay. reliability and lifetime.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
Note 2:
All voltage values are with respect to GND. out into a storage latch.
Note 3:
When these pins are taken below GND or above VDD, they will be
Note 13:
The time period for acquiring the input signal is started by the clamped by internal diodes. This product can handle input currents greater 16th rising clock and it is ended by the rising edge of convert. than 100mA below GND or greater than VDD without latchup.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
Note 4:
Offset and full-gain specifications are measured for a single-ended mode with one or more cycles at SCK and a 10µF capacitive load. A + – IN input with AIN grounded and using the internal 2.5V reference.
Note 15:
The full power bandwidth is the frequency where the output code
Note 5:
Integral linearity is tested with an external 2.55V reference and is swing drops to 3dB with a 2.5VP-P input sine wave. defined as the deviation of a code from the straight line passing through
Note 16:
Maximum clock period guarantees analog performance during the actual endpoints of a transfer curve. The deviation is measured from conversion. Output data can be read with an arbitrarily long clock. the center of quantization band.
Note 17:
VDD = 3.3V, fSAMPLE = 3.5Msps.
Note 6:
Guaranteed by design, not subject to test.
Note 18:
The LTC2356-14 is measured and specified with 14-bit resolution
Note 7:
Recommended operating conditions. (1LSB = 152µV) and the LTC2356-12 is measured and specified with
Note 8:
The analog input range is defined for the voltage difference 12-bit resolution (1LSB = 610µV). between A + – – IN and AIN . Performance is specified with AIN = 1.5V DC while
Note 19:
The sampling capacitor at each input accounts for 4.1pF of the driving A + IN . input capacitance.
Note 9:
The absolute voltage at A + – IN and AIN must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 2356fd For more information www.linear.com/LTC2356-12 5 Document Outline Features Description Applications Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Typical Application Related Parts
timing characteristics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3.3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Rate per Channel l 3.5 MHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l 286 ns tSCK Clock Period (Note 16) l 15.872 10000 ns tCONV Conversion Time (Note 6) 17 18 SCLK cycles t1 Minimum High or Low SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 ns t3 Nearest SCK Edge Before CONV (Note 6) 0 ns t4 Minimum High or Low CONV Pulse Width (Note 6) 4 ns t5 SCK↑ to Sample Mode (Note 6) 4 ns t6 CONV↑ to Hold Mode (Notes 6, 11) 1.2 ns t7 16th SCK↑ to CONV≠ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t8 Delay from SCK to Valid Data (Notes 6, 12) 8 ns t9 SCK↑ to Hi-Z at SDO (Notes 6, 12) 6 ns t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns t12 VREF Settling Time After Sleep-to-Wake Transition (Note 14) 2 ms
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Not the same as aperture delay. Aperture delay is smaller (1ns) may cause permanent damage to the device. Exposure to any Absolute because the 2.2ns delay through the sample-and-hold is subtracted from Maximum Rating condition for extended periods may affect device the CONV to Hold mode delay. reliability and lifetime.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
Note 2:
All voltage values are with respect to GND. out into a storage latch.
Note 3:
When these pins are taken below GND or above VDD, they will be
Note 13:
The time period for acquiring the input signal is started by the clamped by internal diodes. This product can handle input currents greater 16th rising clock and it is ended by the rising edge of convert. than 100mA below GND or greater than VDD without latchup.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
Note 4:
Offset and full-gain specifications are measured for a single-ended mode with one or more cycles at SCK and a 10µF capacitive load. A + – IN input with AIN grounded and using the internal 2.5V reference.
Note 15:
The full power bandwidth is the frequency where the output code
Note 5:
Integral linearity is tested with an external 2.55V reference and is swing drops to 3dB with a 2.5VP-P input sine wave. defined as the deviation of a code from the straight line passing through
Note 16:
Maximum clock period guarantees analog performance during the actual endpoints of a transfer curve. The deviation is measured from conversion. Output data can be read with an arbitrarily long clock. the center of quantization band.
Note 17:
VDD = 3.3V, fSAMPLE = 3.5Msps.
Note 6:
Guaranteed by design, not subject to test.
Note 18:
The LTC2356-14 is measured and specified with 14-bit resolution
Note 7:
Recommended operating conditions. (1LSB = 152µV) and the LTC2356-12 is measured and specified with
Note 8:
The analog input range is defined for the voltage difference 12-bit resolution (1LSB = 610µV). between A + – – IN and AIN . Performance is specified with AIN = 1.5V DC while
Note 19:
The sampling capacitor at each input accounts for 4.1pF of the driving A + IN . input capacitance.
Note 9:
The absolute voltage at A + – IN and AIN must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock cycle later. It is best for CONV to rise half a clock before SCK, when running the clock at rated speed. 2356fd For more information www.linear.com/LTC2356-12 5 Document Outline Features Description Applications Block Diagram Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Revision History Typical Application Related Parts
