Datasheet LTC2364-16 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 16-Bit, 250ksps, Pseudo-Differential Unipolar SAR ADC with 94.7dB SNR |
| Pages / Page | 24 / 1 — FEATURES. DESCRIPTION. 250ksps Throughput Rate. ±0.75LSB INL (Max). … |
| File Format / Size | PDF / 535 Kb |
| Document Language | English |
FEATURES. DESCRIPTION. 250ksps Throughput Rate. ±0.75LSB INL (Max). Guaranteed 16-Bit No Missing Codes
Model Line for this Datasheet
- LTC2364CDE-16#PBF LTC2364CDE-16#PBF LTC2364CDE-16#TRPBF LTC2364CDE-16#TRPBF LTC2364CMS-16#PBF LTC2364CMS-16#PBF LTC2364CMS-16#TRPBF LTC2364CMS-16#TRPBF LTC2364HMS-16#PBF LTC2364HMS-16#PBF LTC2364HMS-16#TRPBF LTC2364HMS-16#TRPBF LTC2364IDE-16#PBF LTC2364IDE-16#PBF LTC2364IDE-16#TRPBF LTC2364IDE-16#TRPBF LTC2364IMS-16#PBF LTC2364IMS-16#PBF LTC2364IMS-16#TRPBF LTC2364IMS-16#TRPBF
Text Version of Document
LTC2364-16 16-Bit, 250ksps, Pseudo- Differential Unipolar SAR ADC with 94.7dB SNR
FEATURES DESCRIPTION
n
250ksps Throughput Rate
The LTC®2364-16 is a low noise, low power, high speed n
±0.75LSB INL (Max)
16-bit successive approximation register (SAR) ADC. n
Guaranteed 16-Bit No Missing Codes
Operating from a 2.5V supply, the LTC2364-16 has a 0V n
Low Power: 3.4mW at 250ksps, 3.4µW at 250sps
to VREF pseudo-differential unipolar input range with VREF n
94.7dB SNR (Typ) at fIN = 2kHz
ranging from 2.5V to 5.1V. The LTC2364-16 consumes n –
120dB THD (Typ) at fIN = 2kHz
only 3.4mW and achieves ±0.75LSB INL maximum, no n Guaranteed Operation to 125°C missing codes at 16 bits with 94.7dB SNR. n 2.5V Supply The LTC2364-16 has a high speed SPI-compatible serial n Pseudo-Differential Unipolar Input Range: 0V to VREF interface that supports 1.8V, 2.5V, 3.3V and 5V logic n VREF Input Range from 2.5V to 5.1V while also featuring a daisy-chain mode. The fast 250ksps n No Pipeline Delay, No Cycle Latency throughput with no cycle latency makes the LTC2364-16 n 1.8V to 5V I/O Voltages ideally suited for a wide variety of high speed applications. n SPI-Compatible Serial I/O with Daisy-Chain Mode An internal oscillator sets the conversion time, easing exter- n Internal Conversion Clock nal timing considerations. The LTC2364-16 automatically n 16-Lead MSOP and 4mm × 3mm DFN Packages powers down between conversions, leading to reduced power dissipation that scales with the sampling rate.
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and n Medical Imaging SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765. n High Speed Data Acquisition n Portable or Compact Instrumentation n Industrial Process Control n Low Power Battery-Operated Instrumentation n ATE
TYPICAL APPLICATION 32k Point FFT fS = 250ksps, fIN = 2kHz
2.5V 1.8V TO 5V 0 SNR = 94.7dB –20 THD = –121dB 10µF 0.1µF SINAD = 94.7dB –40 SFDR = 125dB VREF + V –60 10Ω DD OVDD 0V CHAIN LT®6202 IN+ RDL/SDI –80 – SDO 10nF LTC2364-16 –100 SCK IN– BUSY –120 CNV SAMPLE CLOCK AMPLITUDE (dBFS) REF GND –140 236416 TA01a 2.5V TO 5.1V –160 47µF (X5R, 0805 SIZE) –180 0 25 50 75 100 125 FREQUENCY (kHz) 236416 TA01b 236416fa 1 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY REFERENCE INPUT DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION TIMING DIAGRAMS BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
FEATURES DESCRIPTION
n
250ksps Throughput Rate
The LTC®2364-16 is a low noise, low power, high speed n
±0.75LSB INL (Max)
16-bit successive approximation register (SAR) ADC. n
Guaranteed 16-Bit No Missing Codes
Operating from a 2.5V supply, the LTC2364-16 has a 0V n
Low Power: 3.4mW at 250ksps, 3.4µW at 250sps
to VREF pseudo-differential unipolar input range with VREF n
94.7dB SNR (Typ) at fIN = 2kHz
ranging from 2.5V to 5.1V. The LTC2364-16 consumes n –
120dB THD (Typ) at fIN = 2kHz
only 3.4mW and achieves ±0.75LSB INL maximum, no n Guaranteed Operation to 125°C missing codes at 16 bits with 94.7dB SNR. n 2.5V Supply The LTC2364-16 has a high speed SPI-compatible serial n Pseudo-Differential Unipolar Input Range: 0V to VREF interface that supports 1.8V, 2.5V, 3.3V and 5V logic n VREF Input Range from 2.5V to 5.1V while also featuring a daisy-chain mode. The fast 250ksps n No Pipeline Delay, No Cycle Latency throughput with no cycle latency makes the LTC2364-16 n 1.8V to 5V I/O Voltages ideally suited for a wide variety of high speed applications. n SPI-Compatible Serial I/O with Daisy-Chain Mode An internal oscillator sets the conversion time, easing exter- n Internal Conversion Clock nal timing considerations. The LTC2364-16 automatically n 16-Lead MSOP and 4mm × 3mm DFN Packages powers down between conversions, leading to reduced power dissipation that scales with the sampling rate.
APPLICATIONS
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and n Medical Imaging SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765. n High Speed Data Acquisition n Portable or Compact Instrumentation n Industrial Process Control n Low Power Battery-Operated Instrumentation n ATE
TYPICAL APPLICATION 32k Point FFT fS = 250ksps, fIN = 2kHz
2.5V 1.8V TO 5V 0 SNR = 94.7dB –20 THD = –121dB 10µF 0.1µF SINAD = 94.7dB –40 SFDR = 125dB VREF + V –60 10Ω DD OVDD 0V CHAIN LT®6202 IN+ RDL/SDI –80 – SDO 10nF LTC2364-16 –100 SCK IN– BUSY –120 CNV SAMPLE CLOCK AMPLITUDE (dBFS) REF GND –140 236416 TA01a 2.5V TO 5.1V –160 47µF (X5R, 0805 SIZE) –180 0 25 50 75 100 125 FREQUENCY (kHz) 236416 TA01b 236416fa 1 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY REFERENCE INPUT DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION TIMING DIAGRAMS BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
