Datasheet LTC2421, LTC2422 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 1-/2-Channel 20-Bit µPower No Latency ∆ΣTM ADCs in MSOP-10 |
| Pages / Page | 32 / 10 — APPLICATIO S I FOR ATIO. Converter Operation Cycle. Figure 2. … |
| File Format / Size | PDF / 381 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Converter Operation Cycle. Figure 2. LTC2421/LTC2422 State Transition Diagram
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LTC2421/LTC2422
U U W U APPLICATIO S I FOR ATIO
The LTC2421/LTC2422 are pin compatible with the Once CS is pulled LOW and SCK rising edge is applied, the LTC2401/LTC2402. The devices are designed to allow the device begins outputting the conversion result. There is no user to incorporate either device in the same design with latency in the conversion result. The data output corre- no modifications. While the LTC2421/LTC2422 output word sponds to the conversion just performed. This result is length is 24 bits (as opposed to the 32-bit output of the shifted out on the serial data out pin (SDO) under the LTC2401/LTC2402), its output clock timing can be identi- control of the serial clock (SCK). Data is updated on the cal to the LTC2401/LTC2402. As shown in Figure 1, the falling edge of SCK allowing the user to reliably latch data LTC2421/LTC2422 data output is concluded on the falling on the rising edge of SCK, see Figure 4. The data output edge of the 24th serial clock (SCK). In order to maintain state is concluded once 24 bits are read out of the ADC or drop-in compatibility with the LTC2401/LTC2402, it is when CS is brought HIGH. The device automatically possible to clock the LTC2421/LTC2422 with an additional initiates a new conversion and the cycle repeats. 8 serial clock pulses. This results in 8 additional output bits Through timing control of the CS and SCK pins, the which are always logic HIGH. LTC2421/LTC2422 offer several flexible modes of opera- tion (internal or external SCK and free-running conver-
Converter Operation Cycle
sion modes). These various modes do not require The LTC2421/LTC2422 are low power, delta-sigma ana- programming configuration registers; moreover, they do log-to-digital converters with an easy to use 3-wire serial not disturb the cyclic operation described above. These interface. Their operation is simple and made up of three modes of operation are described in detail in the Serial states. The converter operating cycle begins with the con- Interface Timing Modes section. version, followed by the sleep state and concluded with the data output (see Figure 2). The 3-wire interface consists of CONVERT serial data output (SDO), a serial clock (SCK) and a chip select (CS). SLEEP Initially, the LTC2421/LTC2422 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is re- 1 CS AND duced by an order of magnitude if CS is HIGH. The part SCK remains in the sleep state as long as CS is logic HIGH. The 0 conversion result is held indefinitely in a static shift regis- ter while the converter is in the sleep state. DATA OUTPUT 24212 F02
Figure 2. LTC2421/LTC2422 State Transition Diagram
CS 8 8 8 8 (OPTIONAL) SCK SDO EOC = 1 EOC = 0 DATA OUT EOC = 1 4 STATUS BITS 20 DATA BITS LAST 8 BITS ALWAYS 1 CONVERSION SLEEP DATA OUTPUT CONVERSION 24212 F01
Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402
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U U W U APPLICATIO S I FOR ATIO
The LTC2421/LTC2422 are pin compatible with the Once CS is pulled LOW and SCK rising edge is applied, the LTC2401/LTC2402. The devices are designed to allow the device begins outputting the conversion result. There is no user to incorporate either device in the same design with latency in the conversion result. The data output corre- no modifications. While the LTC2421/LTC2422 output word sponds to the conversion just performed. This result is length is 24 bits (as opposed to the 32-bit output of the shifted out on the serial data out pin (SDO) under the LTC2401/LTC2402), its output clock timing can be identi- control of the serial clock (SCK). Data is updated on the cal to the LTC2401/LTC2402. As shown in Figure 1, the falling edge of SCK allowing the user to reliably latch data LTC2421/LTC2422 data output is concluded on the falling on the rising edge of SCK, see Figure 4. The data output edge of the 24th serial clock (SCK). In order to maintain state is concluded once 24 bits are read out of the ADC or drop-in compatibility with the LTC2401/LTC2402, it is when CS is brought HIGH. The device automatically possible to clock the LTC2421/LTC2422 with an additional initiates a new conversion and the cycle repeats. 8 serial clock pulses. This results in 8 additional output bits Through timing control of the CS and SCK pins, the which are always logic HIGH. LTC2421/LTC2422 offer several flexible modes of opera- tion (internal or external SCK and free-running conver-
Converter Operation Cycle
sion modes). These various modes do not require The LTC2421/LTC2422 are low power, delta-sigma ana- programming configuration registers; moreover, they do log-to-digital converters with an easy to use 3-wire serial not disturb the cyclic operation described above. These interface. Their operation is simple and made up of three modes of operation are described in detail in the Serial states. The converter operating cycle begins with the con- Interface Timing Modes section. version, followed by the sleep state and concluded with the data output (see Figure 2). The 3-wire interface consists of CONVERT serial data output (SDO), a serial clock (SCK) and a chip select (CS). SLEEP Initially, the LTC2421/LTC2422 perform a conversion. Once the conversion is complete, the device enters the sleep state. While in this sleep state, power consumption is re- 1 CS AND duced by an order of magnitude if CS is HIGH. The part SCK remains in the sleep state as long as CS is logic HIGH. The 0 conversion result is held indefinitely in a static shift regis- ter while the converter is in the sleep state. DATA OUTPUT 24212 F02
Figure 2. LTC2421/LTC2422 State Transition Diagram
CS 8 8 8 8 (OPTIONAL) SCK SDO EOC = 1 EOC = 0 DATA OUT EOC = 1 4 STATUS BITS 20 DATA BITS LAST 8 BITS ALWAYS 1 CONVERSION SLEEP DATA OUTPUT CONVERSION 24212 F01
Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402
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