Datasheet LT3471 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Dual 1.3A, 1.2MHz Boost/Inverter in 3mm × 3mm DFN |
| Pages / Page | 16 / 5 — BLOCK DIAGRAM. Figure 1. Block Diagram. OPERATION |
| File Format / Size | PDF / 307 Kb |
| Document Language | English |
BLOCK DIAGRAM. Figure 1. Block Diagram. OPERATION
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Text Version of Document
LT3471
BLOCK DIAGRAM
10 SW1 FB1P 2 + – DRIVER A1 FB1N 1 – RC A2 R Q Q1 + S CC + VIN 1.00V VREF 8 3 0.01Ω ∑ REFERENCE – SHDN/SS1 RAMP LEVEL 9 GENERATOR 11 GND SHIFTER 6 SW2 FB2P 4 + – DRIVER A3 FB2N 5 – RC A4 R Q Q2 + S CC + SHDN/SS2 LEVEL 7 SHIFTER 0.01Ω ∑ – RAMP GENERATOR GND 1.2MHz 3471 F01 OSCILLATOR
Figure 1. Block Diagram OPERATION
The LT3471 uses a constant frequency, current mode the output. Similarly, if the error decreases, less current control scheme to provide excellent line and load regu- is delivered. Each switcher functions independently but lation. Refer to the Block Diagram. At the start of each they share the same oscillator and thus the switchers are oscillator cycle, the SR latch is set, which turns on the always in phase. Enabling the part is done by taking either power switch, Q1 (Q2). A voltage proportional to the switch SHDN/SS pin above 1.8V. Disabling the part is done by current is added to a stabilizing ramp and the resulting grounding both SHDN/SS pins. The soft-start feature of sum is fed into the positive terminal of the PWM compara- the LT3471 allows for clean start-up conditions by limiting tor A2 (A4). When this voltage exceeds the level at the the amount of voltage rise at the output of comparator A1 negative input of A2 (A4), the SR latch is reset, turning and A2, which in turn limits the peak switching current. off the power switch Q1 (Q2). The level at the negative The soft-start feature for each switcher is enabled by input of A2 (A4) is set by the error amplifi er A1 (A3) and slowly ramping that switcher’s SHDN/SS pin, using an is simply an amplifi ed version of the difference between RC network, for example. Typical resistor and capacitor the negative feedback voltage and the positive feedback values are 0.33μF and 4.7k, allowing for a start-up time voltage, usually tied to the reference voltage VREG. In on the order of milliseconds. The LT3471 has a current this manner, the error amplifi er sets the correct peak limit circuit not shown in the Block Diagram. The switch current level to keep the output in regulation. If the error current is constantly monitored and not allowed to exceed amplifi er’s output increases, more current is delivered to the maximum switch current (typically 1.6A). If the switch 3471fb 5
BLOCK DIAGRAM
10 SW1 FB1P 2 + – DRIVER A1 FB1N 1 – RC A2 R Q Q1 + S CC + VIN 1.00V VREF 8 3 0.01Ω ∑ REFERENCE – SHDN/SS1 RAMP LEVEL 9 GENERATOR 11 GND SHIFTER 6 SW2 FB2P 4 + – DRIVER A3 FB2N 5 – RC A4 R Q Q2 + S CC + SHDN/SS2 LEVEL 7 SHIFTER 0.01Ω ∑ – RAMP GENERATOR GND 1.2MHz 3471 F01 OSCILLATOR
Figure 1. Block Diagram OPERATION
The LT3471 uses a constant frequency, current mode the output. Similarly, if the error decreases, less current control scheme to provide excellent line and load regu- is delivered. Each switcher functions independently but lation. Refer to the Block Diagram. At the start of each they share the same oscillator and thus the switchers are oscillator cycle, the SR latch is set, which turns on the always in phase. Enabling the part is done by taking either power switch, Q1 (Q2). A voltage proportional to the switch SHDN/SS pin above 1.8V. Disabling the part is done by current is added to a stabilizing ramp and the resulting grounding both SHDN/SS pins. The soft-start feature of sum is fed into the positive terminal of the PWM compara- the LT3471 allows for clean start-up conditions by limiting tor A2 (A4). When this voltage exceeds the level at the the amount of voltage rise at the output of comparator A1 negative input of A2 (A4), the SR latch is reset, turning and A2, which in turn limits the peak switching current. off the power switch Q1 (Q2). The level at the negative The soft-start feature for each switcher is enabled by input of A2 (A4) is set by the error amplifi er A1 (A3) and slowly ramping that switcher’s SHDN/SS pin, using an is simply an amplifi ed version of the difference between RC network, for example. Typical resistor and capacitor the negative feedback voltage and the positive feedback values are 0.33μF and 4.7k, allowing for a start-up time voltage, usually tied to the reference voltage VREG. In on the order of milliseconds. The LT3471 has a current this manner, the error amplifi er sets the correct peak limit circuit not shown in the Block Diagram. The switch current level to keep the output in regulation. If the error current is constantly monitored and not allowed to exceed amplifi er’s output increases, more current is delivered to the maximum switch current (typically 1.6A). If the switch 3471fb 5
