Datasheet AD7177-2 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers |
| Pages / Page | 61 / 3 — AD7177-2. Data Sheet. TABLE OF CONTENTS |
| Revision | B |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
AD7177-2. Data Sheet. TABLE OF CONTENTS
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AD7177-2 Data Sheet TABLE OF CONTENTS
Features .. 1 CRC Calculation ... 42 Applications ... 1 Integrated Functions .. 44 General Description ... 1 General-Purpose I/O ... 44 Functional Block Diagram .. 1 External Multiplexer Control ... 44 Revision History ... 3 Delay .. 44 Specifications ... 4 24-Bit/32-Bit Conversions... 44 Timing Characteristics .. 7 DOUT_RESET ... 44 Absolute Maximum Ratings .. 9 Synchronization .. 44 Thermal Resistance .. 9 Error Flags ... 45 ESD Caution .. 9 DATA_STAT ... 45 Pin Configuration and Function Descriptions ... 10 IOSTRENGTH ... 46 Typical Performance Characteristics ... 12 Internal Temperature Sensor .. 46 Noise Performance and Resolution .. 18 Grounding and Layout .. 47 Getting Started .. 19 Register Summary .. 48 Power Supplies .. 20 Register Details ... 49 Digital Communication ... 20 Communications Register ... 49 AD7177-2 Reset .. 21 Status Register ... 50 Configuration Overview ... 21 ADC Mode Register ... 51 Circuit Description ... 27 Interface Mode Register .. 52 Buffered Analog Input ... 27 Register Check .. 53 Crosspoint Multiplexer .. 27 Data Register ... 53 AD7177-2 Reference .. 28 GPIO Configuration Register ... 54 Buffered Reference Input ... 29 ID Register... 55 Clock Source ... 29 Channel Register 0 ... 55 Digital Filters ... 30 Channel Register 1 to Channel Register 3 .. 56 Sinc5 + Sinc1 Filter ... 30 Setup Configuration Register 0 .. 57 Sinc3 Filter ... 30 Setup Configuration Register 1 to Setup Configuration Single Cycle Settling ... 31 Register 3 ... 57 Enhanced 50 Hz and 60 Hz Rejection Filters ... 34 Filter Configuration Register 0 ... 58 Operating Modes .. 37 Filter Configuration Register 1 to Filter Configuration Register 3 ... 59 Continuous Conversion Mode ... 37 Offset Register 0 ... 59 Continuous Read Mode ... 38 Offset Register 1 to Offset Register 3 ... 59 Single Conversion Mode ... 39 Gain Register 0.. 59 Standby and Power-Down Modes .. 40 Gain Register 1 to Gain Register 3 ... 59 Calibration ... 40 Outline Dimensions ... 60 Digital Interface .. 41 Ordering Guide .. 60 Checksum Protection... 41 Rev. B | Page 2 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7177-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7177-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 24-BIT/32-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
AD7177-2 Data Sheet TABLE OF CONTENTS
Features .. 1 CRC Calculation ... 42 Applications ... 1 Integrated Functions .. 44 General Description ... 1 General-Purpose I/O ... 44 Functional Block Diagram .. 1 External Multiplexer Control ... 44 Revision History ... 3 Delay .. 44 Specifications ... 4 24-Bit/32-Bit Conversions... 44 Timing Characteristics .. 7 DOUT_RESET ... 44 Absolute Maximum Ratings .. 9 Synchronization .. 44 Thermal Resistance .. 9 Error Flags ... 45 ESD Caution .. 9 DATA_STAT ... 45 Pin Configuration and Function Descriptions ... 10 IOSTRENGTH ... 46 Typical Performance Characteristics ... 12 Internal Temperature Sensor .. 46 Noise Performance and Resolution .. 18 Grounding and Layout .. 47 Getting Started .. 19 Register Summary .. 48 Power Supplies .. 20 Register Details ... 49 Digital Communication ... 20 Communications Register ... 49 AD7177-2 Reset .. 21 Status Register ... 50 Configuration Overview ... 21 ADC Mode Register ... 51 Circuit Description ... 27 Interface Mode Register .. 52 Buffered Analog Input ... 27 Register Check .. 53 Crosspoint Multiplexer .. 27 Data Register ... 53 AD7177-2 Reference .. 28 GPIO Configuration Register ... 54 Buffered Reference Input ... 29 ID Register... 55 Clock Source ... 29 Channel Register 0 ... 55 Digital Filters ... 30 Channel Register 1 to Channel Register 3 .. 56 Sinc5 + Sinc1 Filter ... 30 Setup Configuration Register 0 .. 57 Sinc3 Filter ... 30 Setup Configuration Register 1 to Setup Configuration Single Cycle Settling ... 31 Register 3 ... 57 Enhanced 50 Hz and 60 Hz Rejection Filters ... 34 Filter Configuration Register 0 ... 58 Operating Modes .. 37 Filter Configuration Register 1 to Filter Configuration Register 3 ... 59 Continuous Conversion Mode ... 37 Offset Register 0 ... 59 Continuous Read Mode ... 38 Offset Register 1 to Offset Register 3 ... 59 Single Conversion Mode ... 39 Gain Register 0.. 59 Standby and Power-Down Modes .. 40 Gain Register 1 to Gain Register 3 ... 59 Calibration ... 40 Outline Dimensions ... 60 Digital Interface .. 41 Ordering Guide .. 60 Checksum Protection... 41 Rev. B | Page 2 of 60 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7177-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7177-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 24-BIT/32-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
