Datasheet AD7172-2 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
| Pages / Page | 61 / 1 — Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta. ADC with True Rail-to-Rail … |
| Revision | A |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta. ADC with True Rail-to-Rail Buffers. Data Sheet. AD7172-2. FEATURES
Model Line for this Datasheet
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Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Data Sheet AD7172-2 FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
The AD7172-2 is an intelligent, low noise, low power, multiplexed,
Channel scan data rate of 6.21 kSPS/channel (161 µs settling)
Σ-Δ analog-to-digital converter (ADC) with 2- or 4-channel
Performance specifications
(fully differential/single-ended) inputs for low bandwidth
17.2 noise free bits at 31.25 kSPS
signals. The AD7172-2 has a maximum channel scan rate of
24 noise free bits at 5 SPS
6.21 kSPS (161 µs) for ful y settled data. The output data rates
INL: ±2 ppm of FSR
range from 1.25 SPS to 31.25 kSPS.
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
The AD7172-2 integrates key analog and digital signal condition-
User configurable input channels
ing blocks to allow users to configure an individual setup for each
2 fully differential channels or 4 single-ended channels
analog input channel in use via the SPI. Integrated true rail-to-rail
Crosspoint multiplexer
buffers on the analog inputs and external reference inputs provide
On-chip 2.5 V reference (±2 ppm/°C drift)
easy to drive high impedance inputs. The precision 2.5 V low drift
True rail-to-rail analog and reference input buffers
(2 ppm/°C) band gap internal reference (with an output reference
Internal or external clock
buffer) adds embedded functionality to reduce the external
Power supply
component count.
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
ADC current: 1.5 mA
at a 27.27 SPS output data rate. The user can switch between
Temperature range: −40°C to +105°C
different filter options according to the demands of each channel in
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
the application, with further digital processing functions such as
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSP-
offset and gain calibration registers, which are also configurable on
compatible
a per channel basis. General-purpose inputs/outputs (GPIOs) control external multiplexers synchronous to the ADC conversion
APPLICATIONS
timing.
Process control: PLC/DCS modules
The specified operating temperature range is −40°C to +105°C.
Temperature and pressure measurement
The AD7172-2 is in a 24-lead TSSOP package.
Medical and scientific multichannel instrumentation Chromatography
Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only.
FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD CROSSPOINT AVDD1 MULTIPLEXER 1.8V AVSS 1.8V LDO BUFFERED LDO PRECISION REFERENCE RAIL-TO-RAIL AIN0 AVDD REFERENCE INT INPUT BUFFERS REF CS AIN1 SCLK SERIAL DIGITAL INTERFACE AIN2 Σ-Δ ADC FILTER AND CONTROL DIN DOUT/RDY AIN3 RAIL-TO-RAIL ANALOG INPUT GPIO AND XTAL AND INTERNAL SYNC/ERROR BUFFERS MUX CLOCK OSCILLATOR AIN4 AVSS I/O CONTROL CIRCUITRY TEMPERATURE AD7172-2 SENSOR
001
AVSS GPIO0 GPIO1 XTAL1 XTAL2/CLKIO DGND
12672- Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
The AD7172-2 is an intelligent, low noise, low power, multiplexed,
Channel scan data rate of 6.21 kSPS/channel (161 µs settling)
Σ-Δ analog-to-digital converter (ADC) with 2- or 4-channel
Performance specifications
(fully differential/single-ended) inputs for low bandwidth
17.2 noise free bits at 31.25 kSPS
signals. The AD7172-2 has a maximum channel scan rate of
24 noise free bits at 5 SPS
6.21 kSPS (161 µs) for ful y settled data. The output data rates
INL: ±2 ppm of FSR
range from 1.25 SPS to 31.25 kSPS.
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
The AD7172-2 integrates key analog and digital signal condition-
User configurable input channels
ing blocks to allow users to configure an individual setup for each
2 fully differential channels or 4 single-ended channels
analog input channel in use via the SPI. Integrated true rail-to-rail
Crosspoint multiplexer
buffers on the analog inputs and external reference inputs provide
On-chip 2.5 V reference (±2 ppm/°C drift)
easy to drive high impedance inputs. The precision 2.5 V low drift
True rail-to-rail analog and reference input buffers
(2 ppm/°C) band gap internal reference (with an output reference
Internal or external clock
buffer) adds embedded functionality to reduce the external
Power supply
component count.
AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V
The digital filter allows simultaneous 50 Hz and 60 Hz rejection
ADC current: 1.5 mA
at a 27.27 SPS output data rate. The user can switch between
Temperature range: −40°C to +105°C
different filter options according to the demands of each channel in
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
the application, with further digital processing functions such as
Serial port interface (SPI), QSPI-, MICROWIRE-, and DSP-
offset and gain calibration registers, which are also configurable on
compatible
a per channel basis. General-purpose inputs/outputs (GPIOs) control external multiplexers synchronous to the ADC conversion
APPLICATIONS
timing.
Process control: PLC/DCS modules
The specified operating temperature range is −40°C to +105°C.
Temperature and pressure measurement
The AD7172-2 is in a 24-lead TSSOP package.
Medical and scientific multichannel instrumentation Chromatography
Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only.
FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD CROSSPOINT AVDD1 MULTIPLEXER 1.8V AVSS 1.8V LDO BUFFERED LDO PRECISION REFERENCE RAIL-TO-RAIL AIN0 AVDD REFERENCE INT INPUT BUFFERS REF CS AIN1 SCLK SERIAL DIGITAL INTERFACE AIN2 Σ-Δ ADC FILTER AND CONTROL DIN DOUT/RDY AIN3 RAIL-TO-RAIL ANALOG INPUT GPIO AND XTAL AND INTERNAL SYNC/ERROR BUFFERS MUX CLOCK OSCILLATOR AIN4 AVSS I/O CONTROL CIRCUITRY TEMPERATURE AD7172-2 SENSOR
001
AVSS GPIO0 GPIO1 XTAL1 XTAL2/CLKIO DGND
12672- Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Recommended Linear Regulators DIGITAL COMMUNICATION Accessing the ADC Register Map AD7172-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION BUFFERED ANALOG INPUT CROSSPOINT MULTIPLEXER Fully Differential Inputs Single-Ended Inputs AD7172-2 REFERENCE External Reference Internal Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE INPUT/OUTPUT EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
