Datasheet AD7656A-1 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar, 16-Bit ADC |
| Pages / Page | 29 / 6 — Data Sheet. AD7656A-1. TIMING SPECIFICATIONS. Table 2. Limit at TMIN, … |
| File Format / Size | PDF / 673 Kb |
| Document Language | English |
Data Sheet. AD7656A-1. TIMING SPECIFICATIONS. Table 2. Limit at TMIN, TMAX. Parameter. VDRIVE < 4.75 V. VDRIVE = 4.75 V to 5.25 V
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Data Sheet AD7656A-1 TIMING SPECIFICATIONS
AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the ±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to −16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2. Limit at TMIN, TMAX Parameter VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V Unit Description1
PARALLEL INTERFACE MODE tCONV 3 3 µs typ Conversion time, internal clock tQUIET 150 150 ns min Minimum quiet time required between bus relinquish and start of next conversion tACQ 550 550 ns min Acquisition time t10 25 25 ns min Minimum CONVST x low pulse t1 60 60 ns max CONVST x high to BUSY high tWAKE-UP 2 2 ms max STBY rising edge to CONVST x rising edge, not shown in figures 25 25 µs max Partial power-down mode PARALLEL READ OPERATION t 2 0 0 ns min BUSY to RD delay t3 0 0 ns min CS to RD setup time t4 0 0 ns min CS to RD hold time t5 45 36 ns min RD pulse width t6 45 36 ns max Data access time after RD falling edge t7 10 10 ns min Data hold time after RD rising edge t8 12 12 ns max Bus relinquish time after RD rising edge t9 6 6 ns min Minimum time between reads PARALLEL WRITE OPERATION t11 15 15 ns min WR pulse width t12 0 0 ns min CS to WR setup time t13 5 5 ns min CS to WR hold time t14 5 5 ns min Data setup time before WR rising edge t15 5 5 ns min Data hold after WR rising edge SERIAL INTERFACE MODE fSCLK 18 18 MHz max Frequency of serial read clock t16 12 12 ns max Delay from CS until DOUT x three-state disabled t 2 17 22 22 ns max Data access time after SCLK rising edge/CS falling edge t18 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t19 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t20 10 10 ns min SCLK to data valid hold time after SCLK fal ing edge t21 18 18 ns max CS rising edge to DOUT x high impedance 1 Multifunction pin names may be referenced by their relevant function only. 2 A buffer is used on the DOUT x pins (Pin 5 to Pin 7) for this measurement.
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
002
200µA IOH
11128- Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER SUPPLY SEQUENCING THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS Track-and-Hold Amplifiers Analog Input ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE TYPICAL CONNECTION DIAGRAM DRIVING THE ANALOG INPUTS INTERFACE OPTIONS Parallel Interface (SER/PAR/SEL = 0) SOFTWARE SELECTION OF ADCS Changing the Analog Input Range (H/S SEL = 0) Changing the Analog Input Range (H/S SEL = 1) Serial Interface (SER/PAR/SEL = 1) SERIAL READ OPERATION DAISY-CHAIN MODE (DCEN = 1, SER/PAR/SEL = 1) Standby/Partial Power-Down Modes of Operation(SER/PAR/SEL = 0 or SER/PAR/SEL = 1) APPLICATION HINTS LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7656A-1 TIMING SPECIFICATIONS
AVCC and DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. For the ±4 × VREF range, VDD = 11 V to 16.5 V, and VSS = −11 V to −16.5 V. For the ±2 × VREF range, VDD = 6 V to 16.5 V, and VSS = −6 V to −16.5 V. Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2. Limit at TMIN, TMAX Parameter VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V Unit Description1
PARALLEL INTERFACE MODE tCONV 3 3 µs typ Conversion time, internal clock tQUIET 150 150 ns min Minimum quiet time required between bus relinquish and start of next conversion tACQ 550 550 ns min Acquisition time t10 25 25 ns min Minimum CONVST x low pulse t1 60 60 ns max CONVST x high to BUSY high tWAKE-UP 2 2 ms max STBY rising edge to CONVST x rising edge, not shown in figures 25 25 µs max Partial power-down mode PARALLEL READ OPERATION t 2 0 0 ns min BUSY to RD delay t3 0 0 ns min CS to RD setup time t4 0 0 ns min CS to RD hold time t5 45 36 ns min RD pulse width t6 45 36 ns max Data access time after RD falling edge t7 10 10 ns min Data hold time after RD rising edge t8 12 12 ns max Bus relinquish time after RD rising edge t9 6 6 ns min Minimum time between reads PARALLEL WRITE OPERATION t11 15 15 ns min WR pulse width t12 0 0 ns min CS to WR setup time t13 5 5 ns min CS to WR hold time t14 5 5 ns min Data setup time before WR rising edge t15 5 5 ns min Data hold after WR rising edge SERIAL INTERFACE MODE fSCLK 18 18 MHz max Frequency of serial read clock t16 12 12 ns max Delay from CS until DOUT x three-state disabled t 2 17 22 22 ns max Data access time after SCLK rising edge/CS falling edge t18 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t19 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t20 10 10 ns min SCLK to data valid hold time after SCLK fal ing edge t21 18 18 ns max CS rising edge to DOUT x high impedance 1 Multifunction pin names may be referenced by their relevant function only. 2 A buffer is used on the DOUT x pins (Pin 5 to Pin 7) for this measurement.
200µA IOL TO OUTPUT 1.6V PIN CL 25pF
002
200µA IOH
11128- Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER SUPPLY SEQUENCING THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS Track-and-Hold Amplifiers Analog Input ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE TYPICAL CONNECTION DIAGRAM DRIVING THE ANALOG INPUTS INTERFACE OPTIONS Parallel Interface (SER/PAR/SEL = 0) SOFTWARE SELECTION OF ADCS Changing the Analog Input Range (H/S SEL = 0) Changing the Analog Input Range (H/S SEL = 1) Serial Interface (SER/PAR/SEL = 1) SERIAL READ OPERATION DAISY-CHAIN MODE (DCEN = 1, SER/PAR/SEL = 1) Standby/Partial Power-Down Modes of Operation(SER/PAR/SEL = 0 or SER/PAR/SEL = 1) APPLICATION HINTS LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE
