Datasheet AD7961 (Analog Devices) - 4

ManufacturerAnalog Devices
Description16-Bit, 5 MSPS PULSAR® Differential ADC
Pages / Page25 / 4 — Data Sheet. AD7961. SPECIFICATIONS. Table 2. Parameter. Test …
RevisionB
File Format / SizePDF / 629 Kb
Document LanguageEnglish

Data Sheet. AD7961. SPECIFICATIONS. Table 2. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit

Data Sheet AD7961 SPECIFICATIONS Table 2 Parameter Test Conditions/Comments Min Typ Max Unit

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Data Sheet AD7961 SPECIFICATIONS
VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.8 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits ANALOG INPUT Voltage Range VIN+ − VIN− −VREF +VREF V Operating Input Voltage VIN+, VIN− to GND −0.1 VREF + 0.1 V Common-Mode Input Range1 VREF/2 − 0.05 VREF/2 VREF/2 + 0.05 V CMRR fIN = 500 kHz 70 dB Input Leakage Current Acquisition phase 60 nA THROUGHPUT Complete Cycle 200 ns Throughput Rate 0 5 MSPS DC ACCURACY No Missing Codes 16 Bits Integral Linearity Error −0.55 ±0.2 +0.55 LSB Differential Linearity Error −0.25 ±0.14 +0.25 LSB Transition Noise 0.5 LSB Zero Error −2.5 +2.5 LSB Zero Error Drift1 −0.25 ±0.01 +0.25 ppm/°C Gain Error −8.5 ±1 +8.5 LSB Gain Error Drift1 −0.5 ±0.05 +0.5 ppm/°C Power Supply Sensitivity2 VDD1 = 5 V ± 5% ±0.25 LSB VDD2 = 1.8 V ± 5% ±0.5 LSB AC ACCURACY fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Dynamic Range 95 96 dB Signal-to-Noise Ratio 94.5 95.5 dB Spurious-Free Dynamic Range 118 dB Total Harmonic Distortion −116 dB Signal-to-Noise-and-Distortion Ratio 94 95 dB fIN = 1 kHz, −0.5 dBFS, VREF = 4.096 V Dynamic Range 94 95 dB Signal-to-Noise Ratio 93.5 94.5 dB Spurious-Free Dynamic Range 114 dB Total Harmonic Distortion −112 dB Signal-to-Noise-and-Distortion Ratio 93 94 dB −3 dB Input Bandwidth3 EN2 = 0 28 MHz Oversampled Dynamic Range4 OSR = 256, REF = 5 V 115 dB Aperture Delay5 1.6 ns Aperture Jitter5 1 ps REFERENCE BUFFER REFIN Input Voltage Range1 2.042 2.048 2.054 V REF Output Voltage Range REF at 25°C, EN3 to EN0 = XX01 or 4.086 4.096 4.106 V XX10 Line Regulation VDD1 = 5 V ± 5%, VDD2 = 1.8 V ± 5% ±20 µV Gain Drift1 −25 ±4 +25 ppm/°C Rev. B | Page 3 of 24 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Information Transfer Function Analog Inputs Typical Applications Voltage Reference Options Wake-Up Time from Power-Down and Snooze Modes Power Supply Power-Up Digital Interface Conversion Control Echoed Clock Interface Mode Self Clocked Mode Applications Information Layout Evaluating AD7961 Performance Outline Dimensions Ordering Guide
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