Datasheet AD9484 (Analog Devices) - 5

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AD9484 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2. Parameter 1 , 2 Temp Min Typ Max Unit
SNR fIN = 30.3 MHz 25°C 47.0 dBFS fIN = 70.3 MHz 25°C 47.0 dBFS fIN = 100.3 MHz 25°C 47.0 dBFS Full 46.5 dBFS fIN = 250.3 MHz 25°C 47.0 dBFS fIN = 450.3 MHz 25°C 46.9 dBFS SINAD fIN = 30.3 MHz 25°C 47.0 dBFS fIN = 70.3 MHz 25°C 47.0 dBFS fIN = 100.3 MHz 25°C 47.0 dBFS Full 46.4 dBFS fIN = 250.3 MHz 25°C 47.0 dBFS fIN = 450.3 MHz 25°C 46.9 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30.3 MHz 25°C 7.5 Bits fIN = 70.3 MHz 25°C 7.5 Bits fIN = 100.3 MHz 25°C 7.5 Bits fIN = 250.3 MHz 25°C 7.5 Bits fIN = 450.3 MHz 25°C 7.5 Bits WORST HARMONIC (SECOND or THIRD) fIN = 30.3 MHz 25°C −87 dBc fIN = 70.3 MHz 25°C −86 dBc fIN = 100.3 MHz 25°C −87 dBc Full −75 dBc fIN = 250.3 MHz 25°C 83 dBc fIN = 450.3 MHz 25°C 70 dBc SFDR fIN = 30.3 MHz 25°C 82 dBc fIN = 70.3 MHz 25°C 81 dBc fIN = 100.3 MHz 25°C 82 dBc Full 75 dBc fIN = 250.3 MHz 25°C 79 dBc fIN = 450.3 MHz 25°C 70 dBc WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD) fIN = 30.3 MHz 25°C −82 dBc fIN = 70.3 MHz 25°C −81 dBc fIN = 100.3 MHz 25°C −82 dBc Full −75 dBc fIN = 250.3 MHz 25°C 79 dBc fIN = 450.3 MHz 25°C 77 dBc TWO-TONE IMD fIN1 = 119.5 MHz, fIN2 = 122.5 MHz 25°C −77 dBc ANALOG INPUT BANDWIDTH Full Power 25°C 1 GHz 1 All ac specifications tested by driving CLK+ and CLK− differentially. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. A | Page 4 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT AND VOLTAGE REFERENCE Differential Input Configurations CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS Digital Outputs and Timing Output Data Rate and Pinout Configuration Out-of-Range (OR) TIMING VREF AD9484 CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE