Datasheet AD9262 (Analog Devices) - 10

AD9262 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T + D B D T F D A A D E K ND ND D –B + – + N N D IL E D N N D ND S B CL CG AG AV VI VI AV CF VR AV VI VI AV AG RE CS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CLK– 1 PIN 1 48 SCLK INDICATOR CVDD 2 47 SDIO D0B 3 46 ORA D1B 4 45 D15A D2B 5 44 D14A AD9262 DVDD 6 43 DVDD DGND 7 CMOS OUTPUTS 42 DGND DRVDD 8 41 DRVDD D3B 9 TOP VIEW 40 D13A D4B 10 (Not to Scale) 39 D12A D5B 11 38 D11A D6B 12 37 D10A D7B 13 36 D9A D8B 14 35 D8A D9B 15 34 D7A D10B 16 33 D6A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 B A A A A A A 1B D O ND DD D1 D0 D1 D2 D3 D4 D5 D12B D13B D14B D15B OR VD DC DG DV DR NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB
3
INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
00 2-
THE THERMAL CAPACITY OF THE PACKAGE.
77 07 Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 to 5, 9 to 21 D0B to D15B Channel B Data Output Pins. D0B is the LSB and D15B is the MSB. 6, 25, 43 DVDD Digital Supply (1.8 V). 7, 24, 42 DGND Digital Ground. 8, 23, 41 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 22 ORB Channel B Overrange Indicator. 26 DCO Data Clock Output. 27 to 40, 44, 45 D0A to D15A Channel A Data Output Pins. D0A is the LSB and D15A is the MSB. 46 ORA Channel A Overrange Indicator. 47 SDIO Serial Port Interface Data Input/Output. 48 SCLK Serial Port Interface Clock. 49 CSB Serial Port Interface Chip Select Active Low. 50 RESET Chip Reset. 51, 62 AGND Analog Ground. 52, 55, 58, 61 AVDD Analog Supply (1.8 V). 53 VIN+A Channel A Analog Input (+). 54 VIN−A Channel A Analog Input (−). 56 VREF Voltage Reference Input. 57 CFILT Noise Limiting Filter Capacitor. 59 VIN+B Channel B Analog Input (+). 60 VIN−B Channel B Analog Input (−). 63 CGND Clock Ground. 64 CLK+ Clock Input (+). 65 (EPAD) Exposed pad (EPAD) Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The exposed pad must be soldered to ground. Rev. A | Page 9 of 32 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9262BCPZ AD9262BCPZ-5 AD9262BCPZ-10 Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses DC and Quadrature Error Correction (QEC) LO Leakage (DC) Correction QEC and DC Correction Range Digital Outputs Digital Output Format Interleaved Outputs Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Applications Information Filtering Requirement Memory Map Memory Map Definitions Outline Dimensions Ordering Guide