10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,1.8 V Analog-to-Digital ConverterData SheetAD9609FEATURESFUNCTIONAL BLOCK DIAGRAM1.8 V analog supply operationAVDDGNDSDIO SCLKCSBDRVDD1.8 V to 3.3 V output supply SNRRBIASSPI61.5 dBFS at 9.7 MHz inputVCMROR61.0 dBFS at 200 MHz inputPROGRAMMING DATAFFED9 (MSB)SFDRUVIN+SADCOCORET B75 dBc at 9.7 MHz inputVIN–CMUD0 (LSB)TP73 dBc at 200 MHz inputOUDCOLow powerVREF45 mW at 20 MSPSSENSE76 mW at 80 MSPSREFAD9609SELECTDifferential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuitDIVIDEMODEBYDCSCONTROLS1 TO 82 V p-p differential analog input DNL = ±0.10 LSB 001 Serial port control optionsCLK+ CLK–PDWNDFSMODE 08541- Offset binary, gray code, or twos complement data format Figure 1. Optional clock duty cycle stabilizerPRODUCT HIGHLIGHTSInteger 1-to-8 input clock divider 1. The AD9609 operates from a single 1.8 V analog power Built-in selectable digital test pattern generation supply and features a separate digital output driver supply Energy-saving power-down modes to accommodate 1.8 V to 3.3 V logic families. Data clock out with programmable clock and data alignment 2. The sample-and-hold circuit maintains excel ent performance