Datasheet AD9251 (Analog Devices)

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9251 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIO SCLK CSB 1.8 V to 3.3 V output supply SNR SPI 74.3 dBFS at 9.7 MHz input ORA R 71.5 dBFS at 200 MHz input FFE VIN+A PROGRAMMING DATA D13A S U SFDR ADC O T B VIN–A CM U D0A 93 dBc at 9.7 MHz input TP 80 dBc at 200 MHz input OU DCOA VREF Low power TION SENSE 33 mW per channel at 20 MSPS DRVDD OP AD9251 X REF 73 mW per channel at 80 MSPS VCM U SELECT M ORB Differential input with 700 MHz bandwidth RBIAS R On-chip voltage reference and sample-and-hold circuit FFE VIN–B D13B S U O 2 V p-p differential analog input ADC T B VIN+B CM U D0B DNL = ±0.45 LSB TP OU Serial port control options DCOB Offset binary, gray code, or twos complement data format DIVIDE DUTY CYCLE MODE Optional clock duty cycle stabilizer 1 TO 8 STABILIZER CONTROLS
001
Integer 1-to-8 input clock divider CLK+ CLK– SYNC DCS PDWN DFS OEB
07938-
Data output multiplex option
Figure 1.
Built-in selectable digital test pattern generation Energy-saving power-down modes PRODUCT HIGHLIGHTS Data clock out with programmable clock and data
1. The AD9251 operates from a single 1.8 V analog power
alignment
supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.
APPLICATIONS
2. The patented sample-and-hold circuit maintains excellent
Communications
performance for input frequencies up to 200 MHz and is
Diversity radio systems
designed for low cost, low power, and ease of use.
Multimode digital receivers
3. A standard serial port interface supports various product
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
features and functions, such as data output formatting,
I/Q demodulation systems
internal clock divider, power-down, DCO/DATA timing
Smart antenna systems
and offset adjustments, and voltage reference modes.
Battery-powered instruments
4. The AD9251 is packaged in a 64-lead RoHS compliant
Hand held scope meters
LFCSP that is pin compatible with the AD9268 16-bit
Portable medical imaging
ADC, the AD9258 14-bit ADC, the AD9231 12-bit ADC,
Ultrasound
and the AD9204 10-bit ADC, enabling a simple migration
Radar/LIDAR
path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE