Datasheet AD7262 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators |
| Pages / Page | 33 / 4 — Data Sheet. AD7262. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. … |
| Revision | C |
| File Format / Size | PDF / 896 Kb |
| Document Language | English |
Data Sheet. AD7262. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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Data Sheet AD7262 SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS and fSCLK = 40 MHz for AD7262, fSAMPLE = 500 kSPS and fSCLK = 20 MHz for AD7262-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1 fIN = 100 kHz sine wave Signal-to-Noise Ratio (SNR)2 70 73 dB PGA gain setting = 2 Signal-to-(Noise + Distortion) Ratio 70 72 dB (SINAD)2 Total Harmonic Distortion (THD)2 −85 −77 dB Spurious-Free Dynamic Range (SFDR)2 −97 dB Common-Mode Rejection Ratio (CMRR)3 −76 dB For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 ADC-to-ADC Isolation3 −90 dB Bandwidth3 1.2 MHz @ −3 dB; PGA gain setting = 128 1.7 MHz @ −3 dB; PGA gain setting = 2 DC ACCURACY Resolution 12 Bits Integral Nonlinearity2 ±0.5 ±1 LSB Differential Nonlinearity2 ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits Positive Full-Scale Error2 ±0.122 ±0.305 % FSR Pregain calibration ±0.018 % FSR Postgain calibration Positive Full-Scale Error Match ±0.061 % FSR Zero Code Error2 ±0.092 ±0.244 % FSR Preoffset and pregain calibration ±0.012 % FSR Postoffset and postgain calibration Zero Code Error Match ±0.061 % FSR Negative Full-Scale Error2 ±0.122 ±0.305 % FSR Pregain calibration ±0.018 % FSR Postgain calibration Negative Full-Scale Error Match ±0.061 % FSR Zero Code Error Drift 2.5 µV/°C ANALOG INPUT Input Voltage Range, VIN+ and VIN− V V VCM = AVCC/2; PGA gain setting ≥ 2 V REF ± CM 2 × Gain Common-Mode Voltage Range, VCM VCM − 100 mV VCM + 100 mV V VCM = 2; PGA gain setting = 1; see Figure 19 4 (VCC/2) − 0.4 (VCC/2) + 0.2 V VCM = AVCC/2; PGA gain setting = 2 (VCC/2) − 0.4 (VCC/2) + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 (VCC/2) − 0.6 (VCC/2) + 0.8 V VCM = AVCC/2; PGA gain setting ≥ 48 DC Leakage Current ±0.001 ±1 µA Input Capacitance3 5 pF Input Impedance3 1 GΩ REFERENCE INPUT/OUTPUT Reference Output Voltage 5 2.495 2.5 2.505 V 2.5 V ± 5 mV max @ 25°C Reference Input Voltage Range 2.5 V DC Leakage Current ±0.3 ±1 µA External reference applied to Pin VREFA/Pin VREFB Input Capacitance3 20 pF VREFA, VREFB Output Impedance3 4 Ω Reference Temperature Coefficient 20 ppm/°C VREF Noise3 20 µV rms Rev. B | Page 3 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7262 SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSAMPLE = 1 MSPS and fSCLK = 40 MHz for AD7262, fSAMPLE = 500 kSPS and fSCLK = 20 MHz for AD7262-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1 fIN = 100 kHz sine wave Signal-to-Noise Ratio (SNR)2 70 73 dB PGA gain setting = 2 Signal-to-(Noise + Distortion) Ratio 70 72 dB (SINAD)2 Total Harmonic Distortion (THD)2 −85 −77 dB Spurious-Free Dynamic Range (SFDR)2 −97 dB Common-Mode Rejection Ratio (CMRR)3 −76 dB For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 ADC-to-ADC Isolation3 −90 dB Bandwidth3 1.2 MHz @ −3 dB; PGA gain setting = 128 1.7 MHz @ −3 dB; PGA gain setting = 2 DC ACCURACY Resolution 12 Bits Integral Nonlinearity2 ±0.5 ±1 LSB Differential Nonlinearity2 ±0.5 ±0.99 LSB Guaranteed no missed codes to 12 bits Positive Full-Scale Error2 ±0.122 ±0.305 % FSR Pregain calibration ±0.018 % FSR Postgain calibration Positive Full-Scale Error Match ±0.061 % FSR Zero Code Error2 ±0.092 ±0.244 % FSR Preoffset and pregain calibration ±0.012 % FSR Postoffset and postgain calibration Zero Code Error Match ±0.061 % FSR Negative Full-Scale Error2 ±0.122 ±0.305 % FSR Pregain calibration ±0.018 % FSR Postgain calibration Negative Full-Scale Error Match ±0.061 % FSR Zero Code Error Drift 2.5 µV/°C ANALOG INPUT Input Voltage Range, VIN+ and VIN− V V VCM = AVCC/2; PGA gain setting ≥ 2 V REF ± CM 2 × Gain Common-Mode Voltage Range, VCM VCM − 100 mV VCM + 100 mV V VCM = 2; PGA gain setting = 1; see Figure 19 4 (VCC/2) − 0.4 (VCC/2) + 0.2 V VCM = AVCC/2; PGA gain setting = 2 (VCC/2) − 0.4 (VCC/2) + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 (VCC/2) − 0.6 (VCC/2) + 0.8 V VCM = AVCC/2; PGA gain setting ≥ 48 DC Leakage Current ±0.001 ±1 µA Input Capacitance3 5 pF Input Impedance3 1 GΩ REFERENCE INPUT/OUTPUT Reference Output Voltage 5 2.495 2.5 2.505 V 2.5 V ± 5 mV max @ 25°C Reference Input Voltage Range 2.5 V DC Leakage Current ±0.3 ±1 µA External reference applied to Pin VREFA/Pin VREFB Input Capacitance3 20 pF VREFA, VREFB Output Impedance3 4 Ω Reference Temperature Coefficient 20 ppm/°C VREF Noise3 20 µV rms Rev. B | Page 3 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN-DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Addressing the On-Chip Registers Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTERS SYSTEM GAIN CALIBRATION MICROPROCESSOR INTERFACING AD7262/AD7262-5 TO ADSP-BF531 APPLICATION HINTS GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
