Datasheet AD7912, AD7922 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 2-Channel, 2.35 V to 5.25 V, 1 MSPS, 12-Bit A/D Converter |
| Pages / Page | 32 / 8 — AD7912/AD7922. TIMING EXAMPLES. Timing Example 2. Timing Example 1. … |
| File Format / Size | PDF / 396 Kb |
| Document Language | English |
AD7912/AD7922. TIMING EXAMPLES. Timing Example 2. Timing Example 1. tCONVERT. SCLK. tQUIET. DOUT. ZERO. CHN. MOD. DB11. DB10. DB2. DB1. DB0
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AD7912/AD7922 TIMING EXAMPLES Timing Example 2
Figure 6 and Figure 7 show some of the timing parameters from The AD7922 can also operate with slower clock frequencies. As the Timing Specifications section. shown in Figure 7, when fSCLK = 5 MHz and the throughput rate is 315 kSPS, the cycle time is
Timing Example 1
As shown in Figure 7, when fSCLK = 18 MHz and the throughput t2 + 12.5(1/fSCLK) + tACQ = 3.17 µs is 1 MSPS, the cycle time is With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the t2 + 12.5(1/fSCLK) + tACQ = 1 µs requirement of 290 ns for tACQ. With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where requirement of 290 ns for tACQ. t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET, satisfying the minimum requirement of 30 ns. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 126 ns for tQUIET, In this example, as with other slower clock values, the signal satisfying the minimum requirement of 30 ns. might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t t 7 5 t t t 10 3 4 tQUIET DOUT Z ZERO CHN MOD DB11 DB10 DB2 DB1 DB0 THREE-STATE t8 t9 THREE-STATE DIN X X CHN STY X X X X X
04351-0-006 Figure 6. AD7922 Serial Interface Timing Diagram
CS tCONVERT t2 B C SCLK 1 2 3 4 5 13 14 15 16 t10 tQUIET 12.5(1/f t SCLK) ACQUISITION 1/THROUGHPUT
04351-0-007 Figure 7. Serial Interface Timing Example Rev. 0 | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7912 SPECIFICATIONS AD7922 SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS DIN INPUT DOUT OUTPUT MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME DAISY-CHAIN MODE DAISY-CHAIN EXAMPLE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7912/AD7922 to TMS320C541 Interface AD7912/AD7922 to ADSP-218x AD7912/AD7922 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING AD7912/AD7922 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7912/AD7922 TIMING EXAMPLES Timing Example 2
Figure 6 and Figure 7 show some of the timing parameters from The AD7922 can also operate with slower clock frequencies. As the Timing Specifications section. shown in Figure 7, when fSCLK = 5 MHz and the throughput rate is 315 kSPS, the cycle time is
Timing Example 1
As shown in Figure 7, when fSCLK = 18 MHz and the throughput t2 + 12.5(1/fSCLK) + tACQ = 3.17 µs is 1 MSPS, the cycle time is With t2 = 10 ns minimum, then tACQ is 664 ns, which satisfies the t2 + 12.5(1/fSCLK) + tACQ = 1 µs requirement of 290 ns for tACQ. With t2 = 10 ns minimum, then tACQ is 295 ns, which satisfies the In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where requirement of 290 ns for tACQ. t10 = 30 ns maximum. This allows a value of 134 ns for tQUIET, satisfying the minimum requirement of 30 ns. In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 126 ns for tQUIET, In this example, as with other slower clock values, the signal satisfying the minimum requirement of 30 ns. might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t t 7 5 t t t 10 3 4 tQUIET DOUT Z ZERO CHN MOD DB11 DB10 DB2 DB1 DB0 THREE-STATE t8 t9 THREE-STATE DIN X X CHN STY X X X X X
04351-0-006 Figure 6. AD7922 Serial Interface Timing Diagram
CS tCONVERT t2 B C SCLK 1 2 3 4 5 13 14 15 16 t10 tQUIET 12.5(1/f t SCLK) ACQUISITION 1/THROUGHPUT
04351-0-007 Figure 7. Serial Interface Timing Example Rev. 0 | Page 8 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7912 SPECIFICATIONS AD7922 SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS DIN INPUT DOUT OUTPUT MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME DAISY-CHAIN MODE DAISY-CHAIN EXAMPLE POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7912/AD7922 to TMS320C541 Interface AD7912/AD7922 to ADSP-218x AD7912/AD7922 to DSP563xx Interface APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING AD7912/AD7922 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
