Datasheet AD7787 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Low Power, 2-Channel 24-Bit Sigma-Delta ADC |
| Pages / Page | 21 / 1 — Low Power, 2-Channel. 24-Bit Sigma-Delta ADC. Data Sheet. AD7787. … |
| Revision | A |
| File Format / Size | PDF / 364 Kb |
| Document Language | English |
Low Power, 2-Channel. 24-Bit Sigma-Delta ADC. Data Sheet. AD7787. FEATURES. APPLICATIONS. Power. Smart transmitters
Model Line for this Datasheet
Text Version of Document
Low Power, 2-Channel 24-Bit Sigma-Delta ADC Data Sheet AD7787 FEATURES APPLICATIONS Power Smart transmitters Supply: 2.5 V to 5.25 V operation Battery applications Normal mode: 75 µA max Portable instrumentation Power-down mode: 1 µA max Sensor measurement RMS noise: 1.1 µV at 9.5 Hz update rate Temperature measurement 19.5-bit p-p resolution (22 bits effective resolution) Pressure measurement Integral nonlinearity: 3.5 ppm typical Weigh scales Simultaneous 50 Hz and 60 Hz rejection 4 to 20 mA loops Internal clock oscillator Rail-to-rail input buffer GENERAL DESCRIPTION VDD monitor channel
The AD7787 is a low power, complete analog front end for low
Temperature range: −40°C to +105°C
frequency measurement applications. It contains a low noise
10-lead MSOP
24-bit Σ-Δ ADC with one differential input and one single-
ended input that can be buffered or unbuffered.
INTERFACE
The device operates from an internal clock. Therefore, the user
3-wire serial
does not have to supply a clock source to the device. The output
SPI®, QSPI™, MICROWIRE™, and DSP compatible
data rate from the part is software programmable and can be
Schmitt trigger on SCLK
varied from 9.5 Hz to 120 Hz, with the rms noise equal to 1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduction in the current consumption. The update rate, cutoff frequency, and settling time scales with the clock frequency. The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP.
FUNCTIONAL BLOCK DIAGRAM GND V REFIN DD AD7787 VDD DOUT/RDY SERIAL INTERFACE DIN AIN1(+) AND
Σ
-
∆
SCLK BUF LOGIC MUX ADC CONTROL AIN1(–) CS AIN2 CLOCK GND
04477-0-001 Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C) Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) Data Register (RS1, RS0 = 1, 1; Power-On/Reset = 0×000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Applications Battery Monitoring Outline Dimensions Ordering Guide
The AD7787 is a low power, complete analog front end for low
Temperature range: −40°C to +105°C
frequency measurement applications. It contains a low noise
10-lead MSOP
24-bit Σ-Δ ADC with one differential input and one single-
ended input that can be buffered or unbuffered.
INTERFACE
The device operates from an internal clock. Therefore, the user
3-wire serial
does not have to supply a clock source to the device. The output
SPI®, QSPI™, MICROWIRE™, and DSP compatible
data rate from the part is software programmable and can be
Schmitt trigger on SCLK
varied from 9.5 Hz to 120 Hz, with the rms noise equal to 1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduction in the current consumption. The update rate, cutoff frequency, and settling time scales with the clock frequency. The part operates with a power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP.
FUNCTIONAL BLOCK DIAGRAM GND V REFIN DD AD7787 VDD DOUT/RDY SERIAL INTERFACE DIN AIN1(+) AND
Σ
-
∆
SCLK BUF LOGIC MUX ADC CONTROL AIN1(–) CS AIN2 CLOCK GND
04477-0-001 Figure 1.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C) Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) Data Register (RS1, RS0 = 1, 1; Power-On/Reset = 0×000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Applications Battery Monitoring Outline Dimensions Ordering Guide
