Datasheet AD7866 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Dual 1MSPS, 12-Bit, 2-Channel SAR ADC with Serial Interface |
| Pages / Page | 25 / 5 — AD7866 |
| Revision | A |
| File Format / Size | PDF / 435 Kb |
| Document Language | English |
AD7866
Model Line for this Datasheet
Text Version of Document
AD7866 TIMING SPECIFICATIONS1(VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.) Limit at Parameter TMIN, TMAX Unit Description
f 2 SCLK 10 kHz min 20 MHz max tCONVERT 16 tSCLK ns max tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 50 ns max Minimum Time between End of Serial Read and Next Falling Edge of CS t2 10 ns min CS to SCLK Setup Time t 3 3 25 ns max Delay from CS until DOUTA and DOUTB Three-State Disabled t 3 4 40 ns max Data Access Time after SCLK Falling Edge. VDRIVE 3 V, CL = 50 pF; VDRIVE < 3 V, CL = 25 pF t5 0.4 tSCLK ns min SCLK Low Pulsewidth t6 0.4 tSCLK ns min SCLK High Pulsewidth t7 10 ns min SCLK to Data Valid Hold Time t 4 8 25 ns max CS Rising Edge to DOUTA, DOUTB, High Impedance t 4 9 10 ns min SCLK Falling Edge to DOUTA, DOUTB, High Impedance 50 ns max SCLK Falling Edge to DOUTA, DOUTB, High Impedance NOTES 1Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the CLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true bus relinquish times of the part and are independent of the bus loading. Specifications subject to change without notice.
200
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
A IOH
Figure 1. Load Circuit for Digital Output Timing Specifications –4– REV. A Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Zero Code Error Zero Code Error Match Positive Gain Error Negative Gain Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio (SNDR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation PSR (Power Supply Rejection) PERFORMANCE CURVES Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT Analog Input Ranges Handling Bipolar Input Signals Transfer Functions Digital Inputs REFERENCE CONFIGURATION OPTIONS MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7866 to ADSP-218x AD7866 to TMS320C541 AD7866 to DSP-563xx APPLICATION HINTS Grounding and Layout Evaluating the AD7866 Performance OUTLINE DIMENSIONS Revision History
f 2 SCLK 10 kHz min 20 MHz max tCONVERT 16 tSCLK ns max tSCLK = 1/fSCLK 800 ns max fSCLK = 20 MHz tQUIET 50 ns max Minimum Time between End of Serial Read and Next Falling Edge of CS t2 10 ns min CS to SCLK Setup Time t 3 3 25 ns max Delay from CS until DOUTA and DOUTB Three-State Disabled t 3 4 40 ns max Data Access Time after SCLK Falling Edge. VDRIVE 3 V, CL = 50 pF; VDRIVE < 3 V, CL = 25 pF t5 0.4 tSCLK ns min SCLK Low Pulsewidth t6 0.4 tSCLK ns min SCLK High Pulsewidth t7 10 ns min SCLK to Data Valid Hold Time t 4 8 25 ns max CS Rising Edge to DOUTA, DOUTB, High Impedance t 4 9 10 ns min SCLK Falling Edge to DOUTA, DOUTB, High Impedance 50 ns max SCLK Falling Edge to DOUTA, DOUTB, High Impedance NOTES 1Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2Mark/Space ratio for the CLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4t8, t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo- lated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times t8 and t9 quoted in the timing characteristics are the true bus relinquish times of the part and are independent of the bus loading. Specifications subject to change without notice.
200
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
A IOH
Figure 1. Load Circuit for Digital Output Timing Specifications –4– REV. A Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS TERMINOLOGY Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Zero Code Error Zero Code Error Match Positive Gain Error Negative Gain Error Track-and-Hold Acquisition Time Signal-to-(Noise + Distortion) Ratio (SNDR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation PSR (Power Supply Rejection) PERFORMANCE CURVES Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT Analog Input Ranges Handling Bipolar Input Signals Transfer Functions Digital Inputs REFERENCE CONFIGURATION OPTIONS MODES OF OPERATION Normal Mode Partial Power-Down Mode Full Power-Down Mode POWER-UP TIMES POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7866 to ADSP-218x AD7866 to TMS320C541 AD7866 to DSP-563xx APPLICATION HINTS Grounding and Layout Evaluating the AD7866 Performance OUTLINE DIMENSIONS Revision History
