Datasheet AD7722 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
| Pages / Page | 25 / 4 — AD7722. A Version. Parameter. Test Conditions/Comments. Min. Typ. Max. … |
| Revision | C |
| File Format / Size | PDF / 478 Kb |
| Document Language | English |
AD7722. A Version. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
AD7722 A Version Parameter Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS (Excluding CLKIN) VINH, Input High Voltage 2.0 V VINL, Input Low Voltage 0.8 V CLOCK INPUT (CLKIN) VINH, Input High Voltage 4.0 V VINL, Input Low Voltage 0.4 V ALL LOGIC INPUTS I ± IN, Input Current VIN = 0 V to DVDD 10 µA CIN, Input Capacitance 10 pF LOGIC OUTPUTS VOH, Output High Voltage |IOUT| = 200 µA 4.0 V VOL, Output Low Voltage |IOUT| = 1.6 mA 0.4 V POWER SUPPLIES AVDD, AVDD1 4.75 5.25 V DVDD 4.75 5.25 V IDD Total from AVDD and DVDD 75 mA Power Consumption 375 mW NOTES 1Operating temperature range is –40°C to +85°C (A Version). 2Measurement Bandwidth = 0.5 × fS; Input Level = –0.05 dB. 3TA = 25°C to 85°C/TA = TMIN to TMAX. 4Applies after calibration at temperature of interest. 5Gain error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin. Specifications subject to change without notice. REV. B –3– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History
LOGIC INPUTS (Excluding CLKIN) VINH, Input High Voltage 2.0 V VINL, Input Low Voltage 0.8 V CLOCK INPUT (CLKIN) VINH, Input High Voltage 4.0 V VINL, Input Low Voltage 0.4 V ALL LOGIC INPUTS I ± IN, Input Current VIN = 0 V to DVDD 10 µA CIN, Input Capacitance 10 pF LOGIC OUTPUTS VOH, Output High Voltage |IOUT| = 200 µA 4.0 V VOL, Output Low Voltage |IOUT| = 1.6 mA 0.4 V POWER SUPPLIES AVDD, AVDD1 4.75 5.25 V DVDD 4.75 5.25 V IDD Total from AVDD and DVDD 75 mA Power Consumption 375 mW NOTES 1Operating temperature range is –40°C to +85°C (A Version). 2Measurement Bandwidth = 0.5 × fS; Input Level = –0.05 dB. 3TA = 25°C to 85°C/TA = TMIN to TMAX. 4Applies after calibration at temperature of interest. 5Gain error excludes reference error. The ADC gain is calibrated w.r.t. the voltage on the REF2 pin. Specifications subject to change without notice. REV. B –3– Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING SPECIFICATIONS PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION PARALLEL MODE PIN FUNCTION DESCRIPTIONS SERIAL MODE PIN FUNCTION DESCRIPTIONS TERMINOLOGY Signal-to-Noise Plus Distortion Ratio (S/(N+D)) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Intermodulation Distortion Pass-Band Ripple Pass-Band Frequency Cutoff Frequency Stop-Band Frequency Stop-Band Attenuation Integral Nonlinearity Differential Nonlinearity Common-Mode Rejection Ratio Unipolar Offset Error Bipolar Offset Error Gain Error Typical Performance Characteristics CIRCUIT DESCRIPTION APPLYING THE AD7722 Analog Input Range Differential Inputs Applying the Reference Input Circuits Clock Generation Varying the Master Clock SYSTEM SYNCHRONIZATION AND CONTROL SYNC Input DVAL Reset Input Power-On Reset Offset and Gain Calibration DATA INTERFACING Parallel Interface SERIAL INTERFACE 2-Channel Multiplexed Operation Serial Interfacing to DSPs OUTLINE DIMENSIONS Revision History
