Datasheet AD9059 (Analog Devices) - 4

ManufacturerAnalog Devices
DescriptionDual 8-Bit, 60 MSPS A/D Converter
Pages / Page13 / 4 — AD9059. SPECIFICATIONS (continued). AD9059BRS. Parameter. Temp. Test …
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File Format / SizePDF / 253 Kb
Document LanguageEnglish

AD9059. SPECIFICATIONS (continued). AD9059BRS. Parameter. Temp. Test Level. Min. Typ. Max. Unit. EXPLANATION OF TEST LEVELS

AD9059 SPECIFICATIONS (continued) AD9059BRS Parameter Temp Test Level Min Typ Max Unit EXPLANATION OF TEST LEVELS

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AD9059 SPECIFICATIONS (continued) AD9059BRS Parameter Temp Test Level Min Typ Max Unit
DIGITAL INPUTS Logic 1 Voltage Full VI 2.0 V Logic 0 Voltage Full VI 0.8 V Logic 1 Current Full VI ±1 µA Logic 0 Current Full VI ±1 µA Input Capacitance 25°C V 4.5 pF Encode Pulsewidth High (tEH) 25°C IV 6.7 166 ns Encode Pulsewidth Low (tEL) 25°C IV 6.7 166 ns DIGITAL OUTPUTS Logic 1 Voltage (VDD = 3 V) Full VI 2.95 V Logic 1 Voltage (VDD = 5 V) Full IV 4.95 V Logic 0 Voltage (VDD = 3 V or 5 V) Full VI 0.05 V Output Coding Offset Binary Code POWER SUPPLY VD Supply Current (VD = 5 V) Full VI 72 92 mA VDD Supply Current (VDD = 3 V)4 Full VI 13 15 mA Power Dissipation5, 6 Full VI 400 505 mW Power-Down Dissipation Full VI 6 12 mW Power Supply Rejection Ratio (PSRR) 25°C I 3 mV/V NOTES 1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 2tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 µA. 3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range. 4Digital supply current based on VDD = 3 V output drive with <10 pF loading under dynamic test conditions. 5Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (VD = 5 V ± 5%, VDD = 3 V ± 5%). 6Typical thermal impedance for the RS style (SSOP) 28-lead package: θJC = 39°C/W, θCA = 70°C/W, and θJA = 109°C/W. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS* Test Level
VD, VDD . 7 V I – 100% production tested. Analog Inputs . –0.5 V to VD + 0.5 V Digital Inputs . –0.5 V to VD + 0.5 V II – 100% production tested at +25°C and sample tested at VREF Input . –0.5 V to VD + 0.5 V specified temperatures. Digital Output Current . 20 mA III – Sample tested only. Operating Temperature . –55°C to +125°C Storage Temperature . –65°C to +150°C IV – Parameter is guaranteed by design and characterization testing. *Stresses above those listed under Absolute Maximum Ratings may cause permanent V – Parameter is a typical value only. damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of VI – 100% production tested at +25°C; guaranteed by design this specification is not implied. Exposure to absolute maximum ratings for extended and characterization testing for industrial temperature range. periods may affect device reliability.
ORDERING GUIDE Model Temperature Range Package Option
AD9059BRS –40°C to +85°C RS-28 AD9059/PCB 25°C Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9059 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9059 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation Applications Evaluation Board OUTLINE DIMENSIONS Revision History
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