Datasheet AD624 (Analog Devices) - 10

ManufacturerAnalog Devices
DescriptionHigh Precision, Low Noise Instrumentation Amplifier
Pages / Page17 / 10 — AD624. NOISE. +VS. LOAD. POWER SUPPLY. GROUND. COMMON-MODE REJECTION. …
RevisionC
File Format / SizePDF / 425 Kb
Document LanguageEnglish

AD624. NOISE. +VS. LOAD. POWER SUPPLY. GROUND. COMMON-MODE REJECTION. INPUT BIAS CURRENTS. –INPUT. G = 200. 100. OUT. AD711. POWER. REFERENCE

AD624 NOISE +VS LOAD POWER SUPPLY GROUND COMMON-MODE REJECTION INPUT BIAS CURRENTS –INPUT G = 200 100 OUT AD711 POWER REFERENCE

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AD624 NOISE +VS
The AD624 is designed to provide noise performance near the theoretical noise floor. This is an extremely important design criteria as the front end noise of an instrumentation amplifier is
AD624
the ultimate limitation on the resolution of the data acquisition system it is being used in. There are two sources of noise in an
LOAD
instrument amplifier, the input noise, predominantly generated by the differential input stage, and the output noise, generated
–V TO S
by the output amplifier. Both of these components are present
POWER SUPPLY
at the input (and output) of the instrumentation amplifier. At
GROUND
the input, the input noise will appear unaltered; the output c. AC-Coupled noise will be attenuated by the closed loop gain (at the output, the output noise will be unaltered; the input noise will be ampli- Figure 31. Indirect Ground Returns for Bias Currents fied by the closed loop gain). Those two noise sources must be Although instrumentation amplifiers have differential inputs, root sum squared to determine the total noise level expected at there must be a return path for the bias currents. If this is not the input (or output). provided, those currents will charge stray capacitances, causing The low frequency (0.1 Hz to 10 Hz) voltage noise due to the the output to drift uncontrollably or to saturate. Therefore, output stage is 10 µV p-p, the contribution of the input stage is when amplifying “floating” input sources such as transformers 0.2 µV p-p. At a gain of 10, the RTI voltage noise would be and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground, (see Figure 31).  2 10  1 µV p-p, + 0.2 ( )2  . The RTO voltage noise would be G 
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output 10.2 µV p-p, 102 + 0.2 G ( ) 2 . These calculations hold for voltage when both inputs are changed by equal amounts. These applications using either internal or external gain resistors. specifications are usually given for a full-range input voltage change and a specified source imbalance. “Common-Mode Rejection Ratio” (CMRR) is a ratio expression while “Common-
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input Mode Rejection” (CMR) is the logarithm of that ratio. For transistors of a dc amplifier. Bias currents are an additional example, a CMRR of 10,000 corresponds to a CMR of 80 dB. source of input error and must be considered in a total error In an instrumentation amplifier, ac common-mode rejection is budget. The bias currents when multiplied by the source resis- only as good as the differential phase shift. Degradation of ac tance imbalance appear as an additional offset voltage. (What is common-mode rejection is caused by unequal drops across of concern in calculating bias current errors is the change in bias differing track resistances and a differential phase shift due to current with respect to signal voltage and temperature.) Input varied stray capacitances or cable capacitances. In many appli- offset current is the difference between the two input bias cur- cations shielded cables are used to minimize noise. This tech- rents. The effect of offset current is an input offset voltage whose nique can create common-mode rejection errors unless the magnitude is the offset current times the source resistance. shield is properly driven. Figures 32 and 33 shows active data guards which are configured to improve ac common-mode
+VS
rejection by “bootstrapping” the capacitances of the input cabling, thus minimizing differential phase shift.
+VS –INPUT AD624 LOAD G = 200 100

V RG AD624 OUT 2 AD711 –V TO S POWER REFERENCE SUPPLY GROUND +INPUT –VS
a. Transformer Coupled Figure 32. Shield Driver, G ≥ 100
+VS +VS –INPUT RG AD712 1 100

AD624 AD624 VOUT LOAD 100

–VS RG2 REFERENCE +INPUT –V TO S POWER –VS SUPPLY GROUND
Figure 33. Differential Shield Driver b. Thermocouple REV. C –9–
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